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HDLC for GBT-SCA communication part of DCS work in CRU project.
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For testing the frequency of Arria 10 Development board
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This component can able to log inside FPGA frequency value, with accuracy upto 2 decimal digits. (Value Format : XXX.XX00)
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This project contains Si5341 internal PLL programming for 240 MHz generation on Reflex Arria10 Board
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Engin Eren / xfitter
GNU General Public License v3.0 onlyarchived 0Updated -
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Declan Millar / delphes
Creative Commons Attribution Share Alike 4.0 InternationalA framework for fast simulation of a generic collider experiment
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Firmware dedicated to the communication with the GBTx ASIC
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This project is for doing more detail simulation for New_MDT_TDC ssh://git@gitlab.cern.ch:7999/yuliang/New_TDC.git
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Demonstration on how a DSP block instantiated as System Generator model is simulated differently in System Generator than (once exported as an IP Core) in Vivado
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