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Weimin Song / YARR
GNU General Public License v2.0 or laterYet Another Rapid Readout
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GBT-SC for FPGA: This module (VHDL) allows performing slow-control of the front-end through GBT links (GBTx and SCA configuration)
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A new time-to-digital converter (TDC) ASIC prototype is required for the ATLAS Monitored Drift Tube (MDT) detector. This the logic part of this ASIC with TMR. The reference version without TMR is ssh://git@gitlab.cern.ch:7999/yuliang/New_TDC.git
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Devdatta Majumder / bdaq53
BSD 3-Clause "New" or "Revised" LicenseDAQ and test system for the RD53A readout chip
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Sebastien Wertz / bdaq53
BSD 3-Clause "New" or "Revised" LicenseDAQ and test system for the RD53A readout chip
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This project facilitates the passage and storage of data from a workstation to an external DDR3 memory device on a Stratix 10 GX FPGA board
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This repository stores the source files and results related to the FPGA programming with Vivado HLS tool
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CLICdp / ASICs / CLICpix2
GNU General Public License v3.0 onlyRTL and verification code of the CLICpix2 chip.
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Old copy of https://ohwr.org/project/svec. That git repository has been rewritten to remove all PCB stuff (it is on EDMS) and to add HDL and software
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Reyhan Ramadhan / peary-firmware
GNU General Public License v3.0 onlyPeary Caribou DAQ firmware
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Ester Maria Silva Jimenez / bdaq53
BSD 3-Clause "New" or "Revised" LicenseDAQ and test system for the RD53A readout chip
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Demonstration on how a DSP block instantiated as System Generator model is simulated differently in System Generator than (once exported as an IP Core) in Vivado
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Karol Krizka / YARR-FW
GNU General Public License v3.0 onlyFirmware for PCIe cards which run with YARR sw.
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