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Backup repository to store code while waiting to solve Gitlab problems with atlas-pc-trig-00
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The BTrain-over-WhiteRabbit project provides a set of IP cores that implement a transport layer to be used for transmission of BTrain-related information over WR network. See project wiki
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sifca / bdaq53
BSD 3-Clause "New" or "Revised" LicenseDAQ and test system for the RD53A readout chip
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Firmware for the na62 first level trigger. It works on a Terasic DE4 board with 8 ethernet connections, 4 of them hosted in two HSMC mezzanines. All the details are described in https://twiki.cern.ch/twiki/bin/viewauth/NA62/TDAQL0tp
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GBT-SC for FPGA: This module (VHDL) allows performing slow-control of the front-end through GBT links (GBTx and SCA configuration)
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Antonio Bergnoli / surf
Lawrence Berkeley National Labs BSD variant licenseA huge VHDL library for FPGA development
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Mohsine Menouni / bdaq53
BSD 3-Clause "New" or "Revised" LicenseDAQ and test system for the RD53A readout chip
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HPTD / tx_phase_aligner
CERN Open Hardware Licence Version 2 - Weakly ReciprocalTransmitter phase aligner for Xilinx transceivers
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Abdelali Slimani Cherif / bdaq53
BSD 3-Clause "New" or "Revised" LicenseDAQ and test system for the RD53 readout chips
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Rafael Goncalves Gama / bdaq53
BSD 3-Clause "New" or "Revised" LicenseDAQ and test system for the RD53 readout chips
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