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Implementation of CALO data processing module using Intel oneAPI HLS

SLAC Ultimate RTL Framework

Transmitter phase aligner for Xilinx transceivers

VFC-HD based backend for the MCOI

Simple project to control Kria Zynq UltraScale+ MPSoC on KV260 development board via AXI interface in Linux User Space using minimal software in Python and C++.

CMS Phase2 RCT HLS Project

Yet Another Rapid Readout

MightyPix1 Software + Firmware based on CLICfast public (https://git.scc.kit.edu/zv1228/clicfast-public)

This repository contains schemes, digital design and documentation of the new MCOI platform, which using Enclustra XU5 module with FPGA ZYNQ (XCZU4EV-SFVC784)

Firmware for PCIe cards which run with YARR sw.

Interface to ADC on CaR Board v1.x, component AD9249

Sources, scripts and generated ip-cores. https://github.com/fpgasystems/davos https://github.com/fpgasystems/fpga-network-stack/