Explore projects
-
-
This repository contains schemes, digital design and documentation of the new MCOI platform, which using Enclustra XU5 module with FPGA ZYNQ (XCZU4EV-SFVC784)
Archived 1Updated -
A simple piece of VHDL that will generate some 8b10b encoded packages for the HGTD altiroc emulator https://gitlab.cern.ch/atlas-hgtd/hgtd-peb/-/blob/master/Demonstration/module%20emulator%20v2/module_emulator_v2.pdf
Updated -
Updated
-
-
Firmware for interfacing the GBTx and the JTAG chain to achieve remote reconfiguration of the Kintex FPGAs in the DB6.
Updated -
Kai Chen / GBT4FELIX
GNU General Public License v3.0 onlyMulti-channel GBT-FPGA core used in FELIX.
Updated -
Firmware dedicated to the communication with the GBTx ASIC
Archived 1Updated -
Jeroen Hegeman / tclink
CERN Open Hardware Licence Version 2 - Weakly ReciprocalTiming Compensated Link
Updated -
Updated
-
HPTD / tx_phase_aligner
CERN Open Hardware Licence Version 2 - Weakly ReciprocalTransmitter phase aligner for Xilinx transceivers
Updated -
An example design for the CMS community which shows the usage of the SLINK sender core. It also contains a core for an SLINK receiver. (This can be used by others but it contains specific elements used in the CMD firmware eco-system)
Updated -
This project is for doing more detail simulation for New_MDT_TDC ssh://git@gitlab.cern.ch:7999/yuliang/New_TDC.git
Archived 1Updated -
The MoCo board is in charge of monitoring and control of the OBDT board. It runs on TM7 hw, in a microTCA crate.
Updated -
LHCb / delphes-srcs
Creative Commons Attribution Share Alike 4.0 InternationalUpdated -
A new time-to-digital converter (TDC) ASIC prototype is required for the ATLAS Monitored Drift Tube (MDT) detector. This the logic part of this ASIC with TMR. The reference version without TMR is ssh://git@gitlab.cern.ch:7999/yuliang/New_TDC.git
Archived 1Updated -
-