Explore projects
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Module for adding timestamp information into the data stream.
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HW IP core for controlling the pulser on the CaR board over an AXI bus
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Firmware for Bunch Length Measurement in the CERN PS.
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Karol Krizka / YARR-FW
GNU General Public License v3.0 onlyFirmware for PCIe cards which run with YARR sw.
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Old copy of https://ohwr.org/project/svec. That git repository has been rewritten to remove all PCB stuff (it is on EDMS) and to add HDL and software
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CLICdp / ASICs / CLICpix2
GNU General Public License v3.0 onlyRTL and verification code of the CLICpix2 chip.
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This project facilitates the passage and storage of data from a workstation to an external DDR3 memory device on a Stratix 10 GX FPGA board
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