Explore projects
-
-
Update Vivado version used developing phase-1 firmware to 2020.1 .
Updated -
HPTD / tx_phase_aligner
CERN Open Hardware Licence Version 2 - Weakly ReciprocalTransmitter phase aligner for Xilinx transceivers
Updated -
Pedro Vicente Leitao / tmrg
GNU General Public License v2.0 or laterTriple Modular Redundancy Generator
Updated -
Risto Pejasinovic / tmrg
GNU General Public License v2.0 or laterTriple Modular Redundancy Generator
Updated -
-
Updated
-
Tower Builder model in System Verilog for integration into VHDL
Updated -
Old copy of https://ohwr.org/project/svec. That git repository has been rewritten to remove all PCB stuff (it is on EDMS) and to add HDL and software
Updated -
Antonio Bergnoli / surf
Lawrence Berkeley National Labs BSD variant licenseA huge VHDL library for FPGA development
Updated -
Ales Svetek / surf
Lawrence Berkeley National Labs BSD variant licenseSLAC Ultimate RTL Framework
Updated -
VFC-HD related files of the S-GEFE (L-GEFE + C-GEFE) test project
Updated -
S-GEFE related files of the S-GEFE (L-GEFE + C-GEFE) test project
Updated