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BST implementation for FPGA

Development of the MGT module for the lpGBT protocol for use in a stratix 10 FPGA (L or H tile)

Peary Caribou DAQ firmware

IP for Caribou Peary firmware: Data FIFO with AXI interface to CPU

SLAC Ultimate RTL Framework

Module for adding timestamp information into the data stream.

HW IP core for controlling the pulser on the CaR board over an AXI bus

Firmware for Bunch Length Measurement in the CERN PS.

Firmware for PCIe cards which run with YARR sw.

Old copy of https://ohwr.org/project/svec. That git repository has been rewritten to remove all PCB stuff (it is on EDMS) and to add HDL and software

This project facilitates the passage and storage of data from a workstation to an external DDR3 memory device on a Stratix 10 GX FPGA board