Explore projects
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Development of the MGT module for the lpGBT protocol for use in a stratix 10 FPGA (L or H tile)
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Ales Svetek / ruckus
Lawrence Berkeley National Labs BSD variant licenseVivado build system
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IP for Caribou Peary firmware: Data FIFO with AXI interface to CPU
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Module for adding timestamp information into the data stream.
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Flavio Pisani / ib_flit_sim
Affero General Public License v1.0Fork of the ib_flit_sim project by Mellanox
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HW IP core for controlling the pulser on the CaR board over an AXI bus
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Kade Gigliotti / vmm_boards_firmware
GNU General Public License v3.0 onlyFirmware used for the readout and configuration of the VMM ASIC, a special chip tailored for the needs of ATLAS NSW upgrade.
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ALICE ITS LS2 upgrade working package 10 (WP10) Readout Unit simulation
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