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HDLC for GBT-SCA communication part of DCS work in CRU project.
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For testing the frequency of Arria 10 Development board
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This component can able to log inside FPGA frequency value, with accuracy upto 2 decimal digits. (Value Format : XXX.XX00)
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This project contains Si5341 internal PLL programming for 240 MHz generation on Reflex Arria10 Board
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Optimized GBT-FPGA : single channel and multi-channel examples on VC709
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cloned from BE-BI/VFC-HD, with public access and WhiteRabbit additions
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Open Source VHDL Verification Component Framework for making structured VHDL testbenches for verification of FPGA and ASIC.
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Simulation of a pixel at the edge of an ATLAS IBL Sensor. Long pixel + Guard Ring structure. The process simulation can produce a 2D or 3D model using the same GDS file and process description in sprocess.
ICWB is use to process the GDS mask file
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Petalinux configuration and binaries for the reference implementation of the White Rabbit PTP Core (https://www.ohwr.org/projects/wr-cores/wiki/Wrpc_core)
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Project containing design files for my experimentation with the GBT link
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