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IPbus example design for Zynq Ultrascale+ development board zcu102
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DAQ supervisory board firmware design for VMM/FPGA-bearing boards. It integrates trigger selection logic, a trigger data processing module and busy logic into a single FPGA that connects to multiple front-end nodes.
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Firmware used for the readout and configuration of the VMM ASIC, a special chip tailored for the needs of ATLAS NSW upgrade.
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Firmware used for the readout and configuration of the VMM ASIC, a special chip tailored for the needs of ATLAS NSW upgrade.
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cloned from BE-BI/VFC-HD, with public access and WhiteRabbit additions
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