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[FS] FELIX Firmware

HDL on Git

DAQ and test system for the RD53 readout chips

GBT-SC for FPGA: This module (VHDL) allows performing slow-control of the front-end through GBT links (GBTx and SCA configuration)

Triple Modular Redundancy Generator

One Repository to rule them all

CMS HGCROC chip common testbench FW repo

Timing Compensated Link

VFC-HD system core

HDL cores library of the BE-BI group

Modules for the instantiation of the DDR3 of the VFC-HD board

BST implementation for FPGA

lpGBT CODEC emulation (Verilog core)

Repository for the Level-0 Muon Barrel

PXI express FMC Carrier Board (SPEXI7U)