Clock and Bitslip bugs
Dear GBT team,
I was recently porting the GBT-FPGA core to the FC7 and noticed two tiny bugs in the code, that you might want to fix. The commit with bugfixes is here.
- In the Kintex7 example design, if disabling the data generator, the tx clock was not connected (as it was generated inside the pattern generator).
- In the MGT bitslip control instance, the bitslip was raised high for 40 clock cycles, instead of just 1.
Hope, I did not do anything wrong:) Good luck and thank you for your work.
Cheers, Mykyta