Improve timing closure for descramblers
Using the lpGBT core in a bigger design I'm running into problems for timing closure related to the scramblers in the lpGBT downlink.
descrambler_58bitOrder58.vhd is reported to not pass timing in a design running it with 320 MHz on a Stratix-10 FPGA.
Looking into the descrambler, I'm wondering if one (or more) of the following could be done to improve the situation:
- Removing the entire reset tree: Instead of a reset, simply shifting in zero data should be equivalent of resetting.
- Removing the reset tree for the
memory_register
: To me it looks like data would be shifted through the scrambler anyways.
These 2 suggestions would possibly lead to an increased reset cycle and a different steering of the descrambler.
Another option to be looked into would be to add an additional level of register from data_i
to data_o
, breaking apart the xnor
chain into 2 segments, leading to a shorter combinatorial logic path (per clock cycle).
Implications of any of the proposed solutions would have to be dealt with appropriately.