Rearrange signal declaration to avoid synthesis warnings on unused signals
Description
When using the lpgbt
core in a Stratix-10 design, upon synthesis Quartus throws the following warnings:
Warning(21570): VHDL warning at lpgbtfpga_decoder.vhd(90): using initial value for 'fec12_encoded_code0_s' since it is never assigned
Warning(21570): VHDL warning at lpgbtfpga_decoder.vhd(91): using initial value for 'fec12_encoded_code1_s' since it is never assigned
Warning(21570): VHDL warning at lpgbtfpga_decoder.vhd(92): using initial value for 'fec12_encoded_code2_s' since it is never assigned
Warning(21570): VHDL warning at lpgbtfpga_decoder.vhd(93): using initial value for 'fec12_encoded_code3_s' since it is never assigned
Warning(21570): VHDL warning at lpgbtfpga_decoder.vhd(94): using initial value for 'fec12_encoded_code4_s' since it is never assigned
Warning(21570): VHDL warning at lpgbtfpga_decoder.vhd(95): using initial value for 'fec12_encoded_code5_s' since it is never assigned
These warnings are thrown since fec12_encoded_code?_s
are declared in the architecture but are never used.
Instead, they are used only in the case of FEC = FEC12
.
The very same is true for fec5_encoded_code?_s
in the case of FEC = FEC5
.
Similarly, the following warnings have the same pathology:
Warning(21570): VHDL warning at lpgbtfpga_deinterleaver.vhd(45): using initial value for 'fec5_data_5g12_s' since it is never assigned
Warning(21570): VHDL warning at lpgbtfpga_deinterleaver.vhd(46): using initial value for 'fec5_fec_5g12_s' since it is never assigned
Warning(21570): VHDL warning at lpgbtfpga_deinterleaver.vhd(59): using initial value for 'fec12_data_s' since it is never assigned
Warning(21570): VHDL warning at lpgbtfpga_deinterleaver.vhd(60): using initial value for 'fec12_fec_s' since it is never assigned
Proposed solution
Instead of declaring these signals as global signals, they should be declared only at the generate
statement where they are needed:
- SIGNAL fec12_encoded_code0_s : std_logic_vector(51 downto 0); --! FEC12 encoded data (code 0)
- SIGNAL fec12_encoded_code1_s : std_logic_vector(51 downto 0); --! FEC12 encoded data (code 1)
- SIGNAL fec12_encoded_code2_s : std_logic_vector(51 downto 0); --! FEC12 encoded data (code 2)
- SIGNAL fec12_encoded_code3_s : std_logic_vector(51 downto 0); --! FEC12 encoded data (code 3)
- SIGNAL fec12_encoded_code4_s : std_logic_vector(51 downto 0); --! FEC12 encoded data (code 4)
- SIGNAL fec12_encoded_code5_s : std_logic_vector(51 downto 0); --! FEC12 encoded data (code 5)
...
BEGIN
...
-- FEC12 decoders
fec12_dec_gen: IF FEC = FEC12 GENERATE
+ SIGNAL fec12_encoded_code0_s : std_logic_vector(51 downto 0); --! FEC12 encoded data (code 0)
+ SIGNAL fec12_encoded_code1_s : std_logic_vector(51 downto 0); --! FEC12 encoded data (code 1)
+ SIGNAL fec12_encoded_code2_s : std_logic_vector(51 downto 0); --! FEC12 encoded data (code 2)
+ SIGNAL fec12_encoded_code3_s : std_logic_vector(51 downto 0); --! FEC12 encoded data (code 3)
+ SIGNAL fec12_encoded_code4_s : std_logic_vector(51 downto 0); --! FEC12 encoded data (code 4)
+ SIGNAL fec12_encoded_code5_s : std_logic_vector(51 downto 0); --! FEC12 encoded data (code 5)
+ BEGIN
fec12_encoded_code0_s <= "0000000000000000" & fec12_data_i(135 downto 134) & fec12_data_i(33 downto 0) WHEN (DATARATE = DATARATE_10G24) ELSE
Similar solutions would also apply for the other signals.