From 12b395ed8e441b040a2136fbff8f0f75b6a27c8e Mon Sep 17 00:00:00 2001
From: Tal Roelof Van Daalen <tal.van.daalen@cern.ch>
Date: Thu, 14 Nov 2019 09:49:02 +0100
Subject: [PATCH 1/3] Adding validation regions to VLQ_Selector and
 regions_dictionary

---
 Root/VLQ_Selector.cxx                         | 132 ++--
 .../PrepareConfigFilesFromTemplate.py         |  25 +-
 python/regions_dictionary_sVLQ.py             | 596 +++++++++++-------
 3 files changed, 418 insertions(+), 335 deletions(-)

diff --git a/Root/VLQ_Selector.cxx b/Root/VLQ_Selector.cxx
index 073b41b..f557aff 100644
--- a/Root/VLQ_Selector.cxx
+++ b/Root/VLQ_Selector.cxx
@@ -256,7 +256,8 @@ bool VLQ_Selector::Init(){
       std::vector<std::string> v_supr_svlq = {"0fjex", "1fjin", "1fjin-0Hex-0Vex"};
       for(const std::string& supr : v_supr_svlq){
 	for(const std::string& lepsuf : ch_lep){
-	  AddVLQSelection(lep_prefix+"3_5jwin-1bin-"+supr+lepsuf, do_runop, do_syst, PRESEL);
+    AddVLQSelection(lep_prefix+"3_5jwin-1bin-"+supr+lepsuf, do_runop, do_syst, PRESEL);
+    AddVLQSelection(lep_prefix+"3_5jwin-1_2bwin-"+supr+lepsuf, do_runop, do_syst, PRESEL);
 	  AddVLQSelection(lep_prefix+"6jin-2bin-"+supr+lepsuf, do_runop, do_syst, PRESEL);
 	}
       }//signal suppressing
@@ -311,124 +312,80 @@ bool VLQ_Selector::Init(){
 
     bool do_syst = true;
 
-    //AddVLQSelection("c-all",do_runop, do_syst, SINGLEVLQ);
-
-    /*
-1a. 3-5j, 1-2b, 0T, >=1L, 0H, >=1V  [target: WTZt ]
-1b. 3-5j, 1-2b, 0T, 0L, 0H, >=1V  [target: WTZt ]
-2a. 3-5j, >=3b, 0T, >=1L, >=1H, 0V [target: WTHt ]
-2b. 3-5j, >=3b, 0T, 0L, >=1H, 0V [target: WTHt ]
-3a. >=6j, 2b, 1 L, 0T, 0H, >=1V [target: ZTZt]
-3b. >=6j, 2b, 0L, 1T, 0H, >=1V [target: ZTZt]
-3c. >=6j, 2b, >=2L+T, 0H, >=1V [target: ZTZt]
-4a. >=6j, >=3b, 1L, 0(T+V), >=1H [target: ZTHt]
-4b. >=6j, >=3b, 0L, 1 (T+V), >=1H [target: ZTHt]
-4c. >=6j, >=3b, >=2 (L+T+V), >=1H [target: ZTHt]
-    */
-
     // Signal regions
-    AddVLQSelection(lep_prefix+"3_5jwin-1_2bwin-1fjin-0Tex-0Hex-1Vin", do_runop, do_syst, SINGLEVLQ);       //SR1
-    AddVLQSelection(lep_prefix+"3_5jwin-1_2bwin-1fjin-0LTex-0Hex-1Vin", do_runop, do_syst, SINGLEVLQ);       //SR1-a
-    AddVLQSelection(lep_prefix+"3_5jwin-1_2bwin-1fjin-0Tex-1Lin-0Hex-1Vin", do_runop, do_syst, SINGLEVLQ); //SR1-b ORIG
 
-    //AddVLQSelection(lep_prefix+"3_5jwin-1bex-1fjin-0Tex-0Hex-1Vin", do_runop, do_syst, SINGLEVLQ);       //SR1
     AddVLQSelection(lep_prefix+"3_5jwin-1bex-1fjin-0LTex-0Hex-1Vin", do_runop, do_syst, SINGLEVLQ);       //SR1-a
     AddVLQSelection(lep_prefix+"3_5jwin-1bex-1fjin-0Tex-1Lin-0Hex-1Vin", do_runop, do_syst, SINGLEVLQ); //SR1-b ORIG
 
-    AddVLQSelection(lep_prefix+"3_5jwin-2bex-1fjin-0Tex-0Hex-1Vin", do_runop, do_syst, SINGLEVLQ);       //SR1
     AddVLQSelection(lep_prefix+"3_5jwin-2bex-1fjin-0LTex-0Hex-1Vin", do_runop, do_syst, SINGLEVLQ);       //SR1-a
     AddVLQSelection(lep_prefix+"3_5jwin-2bex-1fjin-0Tex-1Lin-0Hex-1Vin", do_runop, do_syst, SINGLEVLQ); //SR1-b ORIG
 
-    AddVLQSelection(lep_prefix+"3_5jwin-3bin-1fjin-0Tex-1Hin-0Vex", do_runop, do_syst, SINGLEVLQ);          //SR2
-    AddVLQSelection(lep_prefix+"3_5jwin-3bin-1fjin-0LTex-1Hin-0Vex", do_runop, do_syst, SINGLEVLQ);    //SR2-a
-    AddVLQSelection(lep_prefix+"3_5jwin-3bin-1fjin-0Tex-1Lin-1Hin-0Vex", do_runop, do_syst, SINGLEVLQ);    //SR2-b ORIG
-
-    AddVLQSelection(lep_prefix+"3_5jwin-3bex-1fjin-0Tex-1Hin-0Vex", do_runop, do_syst, SINGLEVLQ);          //SR2
     AddVLQSelection(lep_prefix+"3_5jwin-3bex-1fjin-0LTex-1Hin-0Vex", do_runop, do_syst, SINGLEVLQ);    //SR2-a
     AddVLQSelection(lep_prefix+"3_5jwin-3bex-1fjin-0Tex-1Lin-1Hin-0Vex", do_runop, do_syst, SINGLEVLQ);    //SR2-b ORIG
 
-    AddVLQSelection(lep_prefix+"3_5jwin-4bin-1fjin-0Tex-1Hin-0Vex", do_runop, do_syst, SINGLEVLQ);          //SR2
     AddVLQSelection(lep_prefix+"3_5jwin-4bin-1fjin-0LTex-1Hin-0Vex", do_runop, do_syst, SINGLEVLQ);    //SR2-a
     AddVLQSelection(lep_prefix+"3_5jwin-4bin-1fjin-0Tex-1Lin-1Hin-0Vex", do_runop, do_syst, SINGLEVLQ);    //SR2-b ORIG
 
-    AddVLQSelection(lep_prefix+"6jin-1bex-1fjin-1LTin-0Hex-1Vin", do_runop, do_syst, SINGLEVLQ);           //SR3 ORIG
     AddVLQSelection(lep_prefix+"6jin-1bex-1fjin-1Lex-0Tex-0Hex-1Vin", do_runop, do_syst, SINGLEVLQ);       //SR3-a 
     AddVLQSelection(lep_prefix+"6jin-1bex-1fjin-0Lex-1Tex-0Hex-1Vin", do_runop, do_syst, SINGLEVLQ);       //SR3-b 
     AddVLQSelection(lep_prefix+"6jin-1bex-1fjin-2LTin-0Hex-1Vin", do_runop, do_syst, SINGLEVLQ);       //SR3-c
 
-    AddVLQSelection(lep_prefix+"6jin-2bex-1fjin-1LTin-0Hex-1Vin", do_runop, do_syst, SINGLEVLQ);           //SR3 ORIG
     AddVLQSelection(lep_prefix+"6jin-2bex-1fjin-1Lex-0Tex-0Hex-1Vin", do_runop, do_syst, SINGLEVLQ);       //SR3-a 
     AddVLQSelection(lep_prefix+"6jin-2bex-1fjin-0Lex-1Tex-0Hex-1Vin", do_runop, do_syst, SINGLEVLQ);       //SR3-b 
     AddVLQSelection(lep_prefix+"6jin-2bex-1fjin-2LTin-0Hex-1Vin", do_runop, do_syst, SINGLEVLQ);       //SR3-c
 
-    AddVLQSelection(lep_prefix+"6jin-1_2bwin-1fjin-1LTin-0Hex-1Vin", do_runop, do_syst, SINGLEVLQ);           //SR3 ORIG
-    AddVLQSelection(lep_prefix+"6jin-1_2bwin-1fjin-1Lex-0Tex-0Hex-1Vin", do_runop, do_syst, SINGLEVLQ);       //SR3-a 
-    AddVLQSelection(lep_prefix+"6jin-1_2bwin-1fjin-0Lex-1Tex-0Hex-1Vin", do_runop, do_syst, SINGLEVLQ);       //SR3-b 
-    AddVLQSelection(lep_prefix+"6jin-1_2bwin-1fjin-2LTin-0Hex-1Vin", do_runop, do_syst, SINGLEVLQ);       //SR3-c
-
-    AddVLQSelection(lep_prefix+"6jin-3bin-1fjin-1VTin-1Hin", do_runop, do_syst, SINGLEVLQ);              //SR4-0 ORIG
-
-    AddVLQSelection(lep_prefix+"6jin-3bin-1fjin-1Lex-0VTex-1Hin", do_runop, do_syst, SINGLEVLQ);        //SR4-a
-    AddVLQSelection(lep_prefix+"6jin-3bin-1fjin-0Lex-1VTex-1Hin", do_runop, do_syst, SINGLEVLQ);        //SR4-b
-    AddVLQSelection(lep_prefix+"6jin-3bin-1fjin-2VLTin-1Hin", do_runop, do_syst, SINGLEVLQ);        //SR4-c
-
-    AddVLQSelection(lep_prefix+"6jin-3bex-1fjin-1VTin-1Hin", do_runop, do_syst, SINGLEVLQ);              //SR4-0 ORIG
-
     AddVLQSelection(lep_prefix+"6jin-3bex-1fjin-1Lex-0VTex-1Hin", do_runop, do_syst, SINGLEVLQ);        //SR4-a
     AddVLQSelection(lep_prefix+"6jin-3bex-1fjin-0Lex-1VTex-1Hin", do_runop, do_syst, SINGLEVLQ);        //SR4-b
     AddVLQSelection(lep_prefix+"6jin-3bex-1fjin-2VLTin-1Hin", do_runop, do_syst, SINGLEVLQ);        //SR4-c
 
-    AddVLQSelection(lep_prefix+"6jin-4bin-1fjin-1VTin-1Hin", do_runop, do_syst, SINGLEVLQ);              //SR4-0 ORIG
-
     AddVLQSelection(lep_prefix+"6jin-4bin-1fjin-1Lex-0VTex-1Hin", do_runop, do_syst, SINGLEVLQ);        //SR4-a
     AddVLQSelection(lep_prefix+"6jin-4bin-1fjin-0Lex-1VTex-1Hin", do_runop, do_syst, SINGLEVLQ);        //SR4-b
     AddVLQSelection(lep_prefix+"6jin-4bin-1fjin-2VLTin-1Hin", do_runop, do_syst, SINGLEVLQ);        //SR4-c
 
-    //AddVLQSelection(lep_prefix+"6jin-3bin-1fjin-0Tex-1Lin-1Hin-0Vex", do_runop, do_syst, SINGLEVLQ);       //SR4-b
-    //AddVLQSelection(lep_prefix+"6jin-3bin-1fjin-1VLTin-1Hin", do_runop, do_syst, SINGLEVLQ);               //SR4-c
 
-    // AddVLQSelection(lep_prefix+"6jin-2bex-1fjin-0Tex-0Hex-1Vin", do_runop, do_syst, SINGLEVLQ);             //SR5
-    // AddVLQSelection(lep_prefix+"6jin-3bin-1fjin-0Tex-1Lin-1Hin-1Vin", do_runop, do_syst, SINGLEVLQ);       //SR6
-
-    /*
     // Validation regions
-    // SR1-a
-    AddVLQSelection(lep_prefix+"3_5jwin-1_2bwin-0fjex-0Tex-0Hex-1Vin", do_runop, do_syst, SINGLEVLQ);
-    AddVLQSelection(lep_prefix+"3_5jwin-1_2bwin-1fjin-1Tin-0Hex-0Vex", do_runop, do_syst, SINGLEVLQ);
-
-    //SR1-b
-    AddVLQSelection(lep_prefix+"3_5jwin-1_2bwin-0fjex-0Tex-1Lin-0Hex-1Vin", do_runop, do_syst, SINGLEVLQ);
-    AddVLQSelection(lep_prefix+"3_5jwin-1_2bwin-1fjin-1Tin-0Lex-0Hex-1Vin", do_runop, do_syst, SINGLEVLQ);
-
-    // SR2-a
-    // AddVLQSelection(lep_prefix+"3_5jwin-3bin-0fjex-0Tex-1Hin-0Vex", do_runop, do_syst, SINGLEVLQ);
-    // AddVLQSelection(lep_prefix+"3_5jwin-3bin-1fjin-1Tin-0Hex-0Vex", do_runop, do_syst, SINGLEVLQ);
-
-    // SR2-b
-    AddVLQSelection(lep_prefix+"3_5jwin-3bin-0fjex-0Tex-1Lin-1Hin-0Vex", do_runop, do_syst, SINGLEVLQ);
-    AddVLQSelection(lep_prefix+"3_5jwin-3bin-1fjin-1Tin-0Lex-0Hex-0Vex", do_runop, do_syst, SINGLEVLQ);
-
-    // SR3-a
-    AddVLQSelection(lep_prefix+"6jin-2bex-0fjex-2VTin-0Hex", do_runop, do_syst, SINGLEVLQ);
-    AddVLQSelection(lep_prefix+"6jin-2bex-1fjin-1Tex-0Hex-0Vex", do_runop, do_syst, SINGLEVLQ);
-
-    // SR3-b
-    AddVLQSelection(lep_prefix+"6jin-2bex-0fjex-1LTin-0Hex-1Vin", do_runop, do_syst, SINGLEVLQ);
-    AddVLQSelection(lep_prefix+"6jin-2bex-1fjin-1LTin-0Hex-0Vex", do_runop, do_syst, SINGLEVLQ);
-
-    // SR4-a
-    AddVLQSelection(lep_prefix+"6jin-3bin-0fjex-1VTin-1Hin", do_runop, do_syst, SINGLEVLQ);
-    AddVLQSelection(lep_prefix+"6jin-3bin-1fjin-1VTin-0Hex", do_runop, do_syst, SINGLEVLQ);
-
-    // SR4-b
-    AddVLQSelection(lep_prefix+"6jin-3bin-0fjex-0Tex-1Lin-1Hin-0Vex", do_runop, do_syst, SINGLEVLQ);
-    AddVLQSelection(lep_prefix+"6jin-3bin-1fjin-0Tex-1Lin-0Hex-0Vex", do_runop, do_syst, SINGLEVLQ);
-
-    // SR4-c
-    AddVLQSelection(lep_prefix+"6jin-3bin-0fjex-1VLTin-1Hin", do_runop, do_syst, SINGLEVLQ);
-    AddVLQSelection(lep_prefix+"6jin-3bin-1fjin-1VLTin-0Hex", do_runop, do_syst, SINGLEVLQ);
+    if (m_opt->DoValidnRegions()){
+      AddVLQSelection(lep_prefix+"3_5jwin-1bex-0fjex-0Tex-0Lex-0Hex-1Vin", do_runop, do_syst, SINGLEVLQ);
+      AddVLQSelection(lep_prefix+"3_5jwin-1bex-0fjex-0Tex-1Lin-0Hex-1Vin", do_runop, do_syst, SINGLEVLQ);
+      AddVLQSelection(lep_prefix+"3_5jwin-1bex-1fjin-1LTin-0Hex-0Vex", do_runop, do_syst, SINGLEVLQ);
+      AddVLQSelection(lep_prefix+"3_5jwin-1bex-1fjin-1Tin-0Lex-0Hex-1Vin", do_runop, do_syst, SINGLEVLQ);
+
+      AddVLQSelection(lep_prefix+"3_5jwin-2bex-0fjex-0Tex-0Lex-0Hex-1Vin", do_runop, do_syst, SINGLEVLQ);
+      AddVLQSelection(lep_prefix+"3_5jwin-2bex-0fjex-0Tex-1Lin-0Hex-1Vin", do_runop, do_syst, SINGLEVLQ);
+      AddVLQSelection(lep_prefix+"3_5jwin-2bex-1fjin-1LTin-0Hex-0Vex", do_runop, do_syst, SINGLEVLQ);
+      AddVLQSelection(lep_prefix+"3_5jwin-2bex-1fjin-1Tin-0Lex-0Hex-1Vin", do_runop, do_syst, SINGLEVLQ);
+
+      AddVLQSelection(lep_prefix+"3_5jwin-3bex-0fjex-0Tex-0Lex-1Hin-0Vex", do_runop, do_syst, SINGLEVLQ);
+      AddVLQSelection(lep_prefix+"3_5jwin-3bex-0fjex-0Tex-1Lin-1Hin-0Vex", do_runop, do_syst, SINGLEVLQ);
+      AddVLQSelection(lep_prefix+"3_5jwin-3bex-1fjin-1Tin-0Lex-1Hin-0Vex", do_runop, do_syst, SINGLEVLQ); // TOO HIGH SIGNAL
+      AddVLQSelection(lep_prefix+"3_5jwin-3bex-1fjin-1VLTin-0Hex", do_runop, do_syst, SINGLEVLQ);
+
+      AddVLQSelection(lep_prefix+"3_5jwin-4bin-0fjex-0Tex-0Lex-1Hin-0Vex", do_runop, do_syst, SINGLEVLQ);
+      AddVLQSelection(lep_prefix+"3_5jwin-4bin-0fjex-0Tex-1Lin-1Hin-0Vex", do_runop, do_syst, SINGLEVLQ);
+      AddVLQSelection(lep_prefix+"3_5jwin-4bin-1fjin-1Tin-0Lex-1Hin-0Vex", do_runop, do_syst, SINGLEVLQ); // TOO HIGH SIGNAL
+      AddVLQSelection(lep_prefix+"3_5jwin-4bin-1fjin-1VLTin-0Hex", do_runop, do_syst, SINGLEVLQ);
+
+      AddVLQSelection(lep_prefix+"6jin-1bex-0fjex-1LTex-0Hex-1Vin", do_runop, do_syst, SINGLEVLQ);
+      AddVLQSelection(lep_prefix+"6jin-1bex-0fjex-2LTin-0Hex-1Vin", do_runop, do_syst, SINGLEVLQ);
+      AddVLQSelection(lep_prefix+"6jin-1bex-1fjin-0Tex-0Lex-1Hin-1Vin", do_runop, do_syst, SINGLEVLQ);
+      AddVLQSelection(lep_prefix+"6jin-1bex-1fjin-2LTin-1Hin-0Vex", do_runop, do_syst, SINGLEVLQ);
+
+      AddVLQSelection(lep_prefix+"6jin-2bex-0fjex-1LTex-0Hex-1Vin", do_runop, do_syst, SINGLEVLQ);
+      AddVLQSelection(lep_prefix+"6jin-2bex-0fjex-2LTin-0Hex-1Vin", do_runop, do_syst, SINGLEVLQ);
+      AddVLQSelection(lep_prefix+"6jin-2bex-1fjin-0Tex-0Lex-1Hin-1Vin", do_runop, do_syst, SINGLEVLQ);
+      AddVLQSelection(lep_prefix+"6jin-2bex-1fjin-2LTin-1Hin-0Vex", do_runop, do_syst, SINGLEVLQ);
+
+      AddVLQSelection(lep_prefix+"6jin-3bex-0fjex-1VLTex-1Hin", do_runop, do_syst, SINGLEVLQ);
+      AddVLQSelection(lep_prefix+"6jin-3bex-0fjex-2VLTin-1Hin", do_runop, do_syst, SINGLEVLQ);
+      AddVLQSelection(lep_prefix+"6jin-3bex-1fjin-1VLTex-0Hex", do_runop, do_syst, SINGLEVLQ);
+      AddVLQSelection(lep_prefix+"6jin-3bex-1fjin-2VLTin-0Hex", do_runop, do_syst, SINGLEVLQ);
+
+      AddVLQSelection(lep_prefix+"6jin-4bin-0fjex-1VLTex-1Hin", do_runop, do_syst, SINGLEVLQ);
+      AddVLQSelection(lep_prefix+"6jin-4bin-0fjex-2VLTin-1Hin", do_runop, do_syst, SINGLEVLQ); // TOO HIGH SIGNAL
+      AddVLQSelection(lep_prefix+"6jin-4bin-1fjin-1VLTex-0Hex", do_runop, do_syst, SINGLEVLQ);
+      AddVLQSelection(lep_prefix+"6jin-4bin-1fjin-2VLTin-0Hex", do_runop, do_syst, SINGLEVLQ);
+    }
 
-    */
   }//Single VLQ regions
 
   //======== PAIR VLQ REGIONS =========
@@ -442,7 +399,8 @@ bool VLQ_Selector::Init(){
 
   }//Pair VLQ regions
 
-  if(m_opt->DoFitRegions() || m_opt->DoValidnRegions()){
+
+  if(m_opt->DoFitRegions() /*|| m_opt->DoValidnRegions()*/){
 
     bool do_syst = true;
 
diff --git a/macros/macros_stats/PrepareConfigFilesFromTemplate.py b/macros/macros_stats/PrepareConfigFilesFromTemplate.py
index 69109fd..47ab195 100644
--- a/macros/macros_stats/PrepareConfigFilesFromTemplate.py
+++ b/macros/macros_stats/PrepareConfigFilesFromTemplate.py
@@ -4,7 +4,7 @@ import sys
 import importlib
 
 sys.path.append( os.getenv("ROOTCOREBIN") + "/python/VLQAnalysis/" )
-from VLQ_Samples import *
+from VLQ_Samples_mc import *
 #from regions_dictionary import *
 
 ##------------------------------------------------------
@@ -28,7 +28,9 @@ if(len(sys.argv)<5):
     print "    doZeroLep=TRUE/FALSE use the zero lepton regions"
     print "    doOneLep=TRUE/FALSE use the one lepton regions"
     print "    doOneLepEMu=TRUE/FALSE use the separate e/mu regions in one lepton"
+    print "    doSR=TRUE/FALSE use the search regions"
     print "    doVR=TRUE/FALSE use the validation regions"
+    print "    doPresel=TRUE/FALSE use the preselection regions"
     print "    useBlindingCuts=TRUE/FALSE use the meff blinding cuts"
     print "    discriminant=<name of variable to be used as discriminant> (default is meff)"
     print "    discriminant_title=<title of variable to be used as discriminant> (default is m_{eff} [GeV])"
@@ -78,7 +80,9 @@ useFourTopsAsBack = True
 doZeroLep = False
 doOneLep = False
 doOneLepEMu = False
+doSR = True
 doVR = False
+doPresel = False
 useBlindingCuts = False
 useData = False
 discriminant = "meff"
@@ -121,10 +125,18 @@ for iArg in range(1,len(sys.argv)):
         if splitted[1].upper()=="TRUE": doOneLepEMu = True
         elif splitted[1].upper()=="FALSE": doOneLepEMu = False
         else: printError("Error for DOONELEPEMU")
+    elif(argument=="DOSR"):
+        if splitted[1].upper()=="TRUE": doSR = True
+        elif splitted[1].upper()=="FALSE": doSR = False
+        else: printError("Error for DOSR")
     elif(argument=="DOVR"):
         if splitted[1].upper()=="TRUE": doVR = True
         elif splitted[1].upper()=="FALSE": doVR = False
         else: printError("Error for DOVR")
+    elif(argument=="DOPRESEL"):
+        if splitted[1].upper()=="TRUE": doPresel = True
+        elif splitted[1].upper()=="FALSE": doPresel = False
+        else: printError("Error for DOPRESEL")
     elif(argument=="USEBLINDINGCUTS"):
         if splitted[1].upper()=="TRUE": useBlindingCuts = True
         elif splitted[1].upper()=="FALSE": useBlindingCuts = False
@@ -219,14 +231,19 @@ regModule = importlib.import_module(regDict)
 
 
 if doOneLep:
-    Regions += regModule.fit_regions_1l
+    if doSR:
+        Regions += regModule.fit_regions_1l
     if doVR:
         Regions += regModule.validation_regions_1l#+validation_regions_1l_2b
+    if doPresel:
+        Regions += regModule.preselection_regions_1l
 if doZeroLep:
-    Regions += regModule.fit_regions_0l
+    if doSR:
+        Regions += regModule.fit_regions_0l
     if doVR:
         Regions += regModule.validation_regions_0l
-
+    if doPresel:
+        Regions += regModule.preselection_regions_0l
 
 ##------------------------------------------------------
 ## Creating all the config files
diff --git a/python/regions_dictionary_sVLQ.py b/python/regions_dictionary_sVLQ.py
index cca2b8d..25273c3 100644
--- a/python/regions_dictionary_sVLQ.py
+++ b/python/regions_dictionary_sVLQ.py
@@ -18,21 +18,6 @@
 #
 
 
-reg_1lep3_5jwin1_2bwin1fjin0Tex0Hex1Vin = {
-    'name':"HTX_c1lep3_5jwin1_2bwin1fjin0Tex0Hex1Vin",
-    'legend': "#splitline{1l, 3-5j, 1-2b, #geq1fj}{0h, #geq1v, 0t_{h}}",
-    'binning':"600,700,800,900,1000,1200,1400,1600,1800,3000",
-    'binning_recoVLQ0_m':"600,700,800,900,1000,1100,1200,1300,1400,1500,1600,1700,1800,1900,2000,2200,3000",#,3500,4000,4500,5000",
-    'type':"SIGNAL"
-}
-#  c1lep3_5jwin1_2bwin1fjin0Tex1Lin0Hex1Vin	
-reg_1lep3_5jwin1_2bwin1fjin0Tex1Lin0Hex1Vin = {
-    'name':"HTX_c1lep3_5jwin1_2bwin1fjin0Tex1Lin0Hex1Vin",
-    'legend': "#splitline{1l, 3-5j, 1-2b, #geq1fj}{0h, #geq1v, 0t_{h}, #geq1t_{l}}",
-    'binning':"600,700,800,900,1000,1200,1400,1600,1800,3000",
-    'binning_recoVLQ0_m':"600,700,800,900,1000,1100,1200,1300,1400,1500,1600,1700,1800,1900,2000,2200,3000",#,3500,4000,4500,5000",
-    'type':"SIGNAL"
-}
 reg_1lep3_5jwin1bex1fjin0Tex1Lin0Hex1Vin = {
     'name':"HTX_c1lep3_5jwin1bex1fjin0Tex1Lin0Hex1Vin",
     'legend': "#splitline{1l, 3-5j, 1b, #geq1fj}{0h, #geq1v, 0t_{h}, #geq1t_{l}}",
@@ -47,14 +32,6 @@ reg_1lep3_5jwin2bex1fjin0Tex1Lin0Hex1Vin = {
     'binning_recoVLQ0_m':"600,700,800,900,1000,1100,1200,1300,1400,1500,1600,1700,1800,1900,2000,2200,3000",#,3500,4000,4500,5000",
     'type':"SIGNAL"
 }
-#  c1lep3_5jwin1_2bwin1fjin0LTex0Hex1Vin	
-reg_1lep3_5jwin1_2bwin1fjin0LTex0Hex1Vin = {
-    'name':"HTX_c1lep3_5jwin1_2bwin1fjin0LTex0Hex1Vin",
-    'legend': "#splitline{1l, 3-5j, 1-2b, #geq1fj}{0h, #geq1v, 0(t_{l}+t_{h})}",
-    'binning':"600,700,800,900,1000,1200,1400,1600,1800,3000",
-    'binning_recoVLQ0_m':"600,700,800,900,1000,1100,1200,1300,1400,1500,1600,1700,1800,1900,2000,2200,3000",#,3500,4000,4500,5000",
-    'type':"SIGNAL"
-}
 reg_1lep3_5jwin1bex1fjin0LTex0Hex1Vin = {
     'name':"HTX_c1lep3_5jwin1bex1fjin0LTex0Hex1Vin",
     'legend': "#splitline{1l, 3-5j, 1b, #geq1fj}{0h, #geq1v, 0(t_{l}+t_{h})}",
@@ -69,14 +46,6 @@ reg_1lep3_5jwin2bex1fjin0LTex0Hex1Vin = {
     'binning_recoVLQ0_m':"600,700,800,900,1000,1100,1200,1300,1400,1500,1600,1700,1800,1900,2000,2200,3000",#,3500,4000,4500,5000",
     'type':"SIGNAL"
 }
-#  c1lep3_5jwin3bin1fjin0Tex1Lin1Hin0Vex	
-reg_1lep3_5jwin3bin1fjin0Tex1Lin1Hin0Vex = {
-    'name':"HTX_c1lep3_5jwin3bin1fjin0Tex1Lin1Hin0Vex",
-    'legend': "#splitline{1l, 3-5j, #geq3b, #geq1fj}{#geq1h, 0v, 0t_{h}, #geq1t_{l}}",
-    'binning':"600,700,800,900,1000,1200,1400,1600,1800,3000",
-    'binning_recoVLQ0_m':"600,700,800,900,1000,1100,1200,1300,1400,1500,1600,1700,1800,1900,2000,2200,3000",#2000,2500,3000,3500,4000,4500,5000",
-    'type':"SIGNAL"
-}
 reg_1lep3_5jwin3bex1fjin0Tex1Lin1Hin0Vex = {
     'name':"HTX_c1lep3_5jwin3bex1fjin0Tex1Lin1Hin0Vex",
     'legend': "#splitline{1l, 3-5j, 3b, #geq1fj}{#geq1h, 0v, 0t_{h}, #geq1t_{l}}",
@@ -91,14 +60,6 @@ reg_1lep3_5jwin4bin1fjin0Tex1Lin1Hin0Vex = {
     'binning_recoVLQ0_m':"600,700,800,900,1000,1100,1200,1300,1400,1500,1600,1700,1800,1900,2000,2200,3000",#2000,2500,3000,3500,4000,4500,5000",
     'type':"SIGNAL"
 }
-#  c1lep3_5jwin3bin1fjin0LTex1Hin0Vex	
-reg_1lep3_5jwin3bin1fjin0LTex1Hin0Vex = {
-    'name':"HTX_c1lep3_5jwin3bin1fjin0LTex1Hin0Vex",
-    'legend': "#splitline{1l, 3-5j, #geq3b, #geq1fj}{#geq1h, 0(t_{l}+t_{h}), 0v}",
-    'binning':"600,700,800,900,1000,1200,1400,1600,1800,3000",
-    'binning_recoVLQ0_m':"600,700,800,900,1000,1100,1200,1300,1400,1500,1600,1700,1800,1900,2000,2200,3000",#2000,2500,3000,3500,4000,4500,5000",
-    'type':"SIGNAL"
-}
 reg_1lep3_5jwin3bex1fjin0LTex1Hin0Vex = {
     'name':"HTX_c1lep3_5jwin3bex1fjin0LTex1Hin0Vex",
     'legend': "#splitline{1l, 3-5j, 3b, #geq1fj}{#geq1h, 0(t_{l}+t_{h}), 0v}",
@@ -113,14 +74,6 @@ reg_1lep3_5jwin4bin1fjin0LTex1Hin0Vex = {
     'binning_recoVLQ0_m':"600,700,800,900,1000,1100,1200,1300,1400,1500,1600,1700,1800,1900,2000,2200,3000",#2000,2500,3000,3500,4000,4500,5000",
     'type':"SIGNAL"
 }
-#  c1lep6jin2bex1fjin1Lex0Tex0Hex1Vin	
-reg_1lep6jin1_2bwin1fjin1Lex0Tex0Hex1Vin = {
-    'name':"HTX_c1lep6jin1_2bwin1fjin1Lex0Tex0Hex1Vin",
-    'legend': "#splitline{1l, #geq6j, 1-2b, #geq1fj}{0h, 1t_{l}, 0t_{h}, #geq1v}",
-    'binning':"600,700,800,900,1000,1200,1400,1600,1800,3000",
-    'binning_recoVLQ0_m':"600,700,800,900,1000,1100,1200,1300,1400,1500,1600,1700,1800,1900,2000,2200,3000",#,3500,4000,4500,5000",
-    'type':"SIGNAL"
-}
 reg_1lep6jin1bex1fjin1Lex0Tex0Hex1Vin = {
     'name':"HTX_c1lep6jin1bex1fjin1Lex0Tex0Hex1Vin",
     'legend': "#splitline{1l, #geq6j, 1b, #geq1fj}{0h, 1t_{l}, 0t_{h}, #geq1v}",
@@ -135,15 +88,6 @@ reg_1lep6jin2bex1fjin1Lex0Tex0Hex1Vin = {
     'binning_recoVLQ0_m':"600,700,800,900,1000,1100,1200,1300,1400,1500,1600,1700,1800,1900,2000,2200,3000",#,3500,4000,4500,5000",
     'type':"SIGNAL"
 }
-
-#  c1lep6jin2bex1fjin0Lex1Tex0Hex1Vin	
-reg_1lep6jin1_2bwin1fjin0Lex1Tex0Hex1Vin = {
-    'name':"HTX_c1lep6jin1_2bwin1fjin0Lex1Tex0Hex1Vin",
-    'legend': "#splitline{1l, #geq6j, 1-2b, #geq1fj}{0h, 0t_{l}, 1t_{h}, #geq1v}",
-    'binning':"600,700,800,900,1000,1200,1400,1600,1800,3000",
-    'binning_recoVLQ0_m':"600,700,800,900,1000,1100,1200,1300,1400,1500,1600,1700,1800,1900,2000,2200,3000",#,3500,4000,4500,5000",
-    'type':"SIGNAL"
-}
 reg_1lep6jin1bex1fjin0Lex1Tex0Hex1Vin = {
     'name':"HTX_c1lep6jin1bex1fjin0Lex1Tex0Hex1Vin",
     'legend': "#splitline{1l, #geq6j, 1b, #geq1fj}{0h, 0t_{l}, 1t_{h}, #geq1v}",
@@ -158,14 +102,6 @@ reg_1lep6jin2bex1fjin0Lex1Tex0Hex1Vin = {
     'binning_recoVLQ0_m':"600,700,800,900,1000,1100,1200,1300,1400,1500,1600,1700,1800,1900,2000,2200,3000",#,3500,4000,4500,5000",
     'type':"SIGNAL"
 }
-#  c1lep6jin2bex1fjin2LTin0Hex1Vin
-reg_1lep6jin1_2bwin1fjin2LTin0Hex1Vin = {
-    'name':"HTX_c1lep6jin1_2bwin1fjin2LTin0Hex1Vin",
-    'legend': "#splitline{1l, #geq6j, 1-2b, #geq1fj}{0h, #geq2(t_{l}+t_{h}), #geq1v}",
-    'binning':"600,700,800,900,1000,1200,1400,1600,1800,3000",
-    'binning_recoVLQ0_m':"600,700,800,900,1000,1100,1200,1300,1400,1500,1600,1700,1800,1900,2000,2200,3000",#,3500,4000,4500,5000",
-    'type':"SIGNAL"
-}
 reg_1lep6jin1bex1fjin2LTin0Hex1Vin = {
     'name':"HTX_c1lep6jin1bex1fjin2LTin0Hex1Vin",
     'legend': "#splitline{1l, #geq6j, 1b, #geq1fj}{0h, #geq2(t_{l}+t_{h}), #geq1v}",
@@ -180,30 +116,6 @@ reg_1lep6jin2bex1fjin2LTin0Hex1Vin = {
     'binning_recoVLQ0_m':"600,700,800,900,1000,1100,1200,1300,1400,1500,1600,1700,1800,1900,2000,2200,3000",#,3500,4000,4500,5000",
     'type':"SIGNAL"
 }
-	
-reg_1lep6jin2bex1fjin2VTin0Hex = {
-    'name':"HTX_c1lep6jin2bex1fjin2VTin0Hex",
-    'legend': "#splitline{1l, #geq6j, 2b, #geq1fj}{0h, #geq2(v+t_{h})}",
-    'binning':"600,700,800,900,1000,1200,1400,1600,1800,3000",
-    'binning_recoVLQ0_m':"600,700,800,900,1000,1100,1200,1300,1400,1500,1600,1700,1800,1900,2000,2200,3000",#,3500,4000,4500,5000",
-    'type':"SIGNAL"
-}
-reg_1lep6jin2bex1fjin1LTin0Hex1Vin = {
-    'name':"HTX_c1lep6jin2bex1fjin1LTin0Hex1Vin",
-    'legend': "#splitline{1l, #geq6j, 2b, #geq1fj}{0h, #geq1v, #geq1(t_{l}+t_{h})}",
-    'binning':"600,700,800,900,1000,1200,1400,1600,1800,3000",
-    'binning_recoVLQ0_m':"600,700,800,900,1000,1100,1200,1300,1400,1500,1600,1700,1800,1900,2000,2200,3000",#,3000,3500,4000,4500,5000",
-    'type':"SIGNAL"
-}
-
-#  c1lep6jin3bin1fjin0Lex1VTex1Hin	
-reg_1lep6jin3bin1fjin0Lex1VTex1Hin = {
-    'name':"HTX_c1lep6jin3bin1fjin0Lex1VTex1Hin",
-    'legend': "#splitline{1l, #geq6j, #geq3b, #geq1fj}{#geq1h, 1(v+t_{h}), 0t_{l}}",
-    'binning':"600,700,800,900,1000,1200,1400,1600,1800,3000",
-    'binning_recoVLQ0_m':"600,700,800,900,1000,1100,1200,1300,1400,1500,1600,1700,1800,1900,2000,2200,3000",#,3500,4000,4500,5000",
-    'type':"SIGNAL"
-}
 reg_1lep6jin3bex1fjin0Lex1VTex1Hin = {
     'name':"HTX_c1lep6jin3bex1fjin0Lex1VTex1Hin",
     'legend': "#splitline{1l, #geq6j, 3b, #geq1fj}{#geq1h, 1(v+t_{h}), 0t_{l}}",
@@ -218,14 +130,6 @@ reg_1lep6jin4bin1fjin0Lex1VTex1Hin = {
     'binning_recoVLQ0_m':"600,700,800,900,1000,1100,1200,1300,1400,1500,1600,1700,1800,1900,2000,2200,3000",#,3500,4000,4500,5000",
     'type':"SIGNAL"
 }
-#  c1lep6jin3bin1fjin1Lex0VTex1Hin	
-reg_1lep6jin3bin1fjin1Lex0VTex1Hin = {
-    'name':"HTX_c1lep6jin3bin1fjin1Lex0VTex1Hin",
-    'legend': "#splitline{1l, #geq6j, #geq3b, #geq1fj}{#geq1h, 0(v+t_{h}), 1t_{l}}",
-    'binning':"600,700,800,900,1000,1200,1400,1600,1800,3000",
-    'binning_recoVLQ0_m':"600,700,800,900,1000,1100,1200,1300,1400,1500,1600,1700,1800,1900,2000,2200,3000",#,3500,4000,4500,5000",
-    'type':"SIGNAL"
-}
 reg_1lep6jin3bex1fjin1Lex0VTex1Hin = {
     'name':"HTX_c1lep6jin3bex1fjin1Lex0VTex1Hin",
     'legend': "#splitline{1l, #geq6j, 3b, #geq1fj}{#geq1h, 0(v+t_{h}), 1t_{l}}",
@@ -240,14 +144,6 @@ reg_1lep6jin4bin1fjin1Lex0VTex1Hin = {
     'binning_recoVLQ0_m':"600,700,800,900,1000,1100,1200,1300,1400,1500,1600,1700,1800,1900,2000,2200,3000",#,3500,4000,4500,5000",
     'type':"SIGNAL"
 }
-#  c1lep6jin3bin1fjin2VLTin1Hin	
-reg_1lep6jin3bin1fjin2VLTin1Hin = {
-    'name':"HTX_c1lep6jin3bin1fjin2VLTin1Hin",
-    'legend': "#splitline{1l, #geq6j, #geq3b, #geq1fj}{#geq1h, #geq2(t_{l}+t_{h}+v)}",
-    'binning':"600,700,800,900,1000,1200,1400,1600,1800,3000",
-    'binning_recoVLQ0_m':"600,700,800,900,1000,1100,1200,1300,1400,1500,1600,1700,1800,1900,2000,2200,3000",#,3500,4000,4500,5000",
-    'type':"SIGNAL"
-}
 reg_1lep6jin3bex1fjin2VLTin1Hin = {
     'name':"HTX_c1lep6jin3bex1fjin2VLTin1Hin",
     'legend': "#splitline{1l, #geq6j, 3b, #geq1fj}{#geq1h, #geq2(t_{l}+t_{h}+v)}",
@@ -263,204 +159,416 @@ reg_1lep6jin4bin1fjin2VLTin1Hin = {
     'type':"SIGNAL"
 }
 
-reg_1lep6jin3bin1fjin1VTin1Hin = {
-    'name':"HTX_c1lep6jin3bin1fjin1VTin1Hin",
-    'legend': "#splitline{1l, #geq6j, #geq3b, #geq1fj}{#geq1h, #geq1(v+t_{h})}",
-    'binning':"600,700,800,900,1000,1200,1400,1600,1800,3000",
-    'binning_recoVLQ0_m':"600,700,800,900,1000,1100,1200,1300,1400,1500,1600,1700,1800,1900,2000,2200,3000",#,3500,4000,4500,5000",
-    'type':"SIGNAL"
+#
+#
+# validation regions
+#
+#
+
+reg_1lep3_5jwin1bex0fjex0Tex0Lex0Hex1Vin = {
+    'name':"HTX_c1lep3_5jwin1bex0fjex0Tex0Lex0Hex1Vin",
+    'legend': "1l, 3-5j, 1b, 0fj, 0h, #geq1v, 0t_{h}, 0t_{l}",
+    'binning':"600,800,1000,1400,1600,1800,3000",
+    'binning_recoVLQ0_m':"600,700,800,900,1000,1100,1200,1300,1400,1500,1600,1700,1800,1900,2000,2200,3000",
+    'type':"VALIDATION"
 }
-reg_1lep6jin3bin1fjin0Tex1Lin1Hin0Vex = {
-    'name':"HTX_c1lep6jin3bin1fjin0Tex1Lin1Hin0Vex",
-    'legend': "#splitline{1l, #geq6j, #geq3b, #geq1fj}{#geq1h, 0v, 0t_{h}, #geq1t_{l}}",
-    'binning':"600,700,800,900,1000,1200,1400,1600,1800,3000",
-    'binning_recoVLQ0_m':"600,700,800,900,1000,1100,1200,1300,1400,1500,1600,1700,1800,1900,2000,2200,3000",#,3500,4000,4500,5000",
-    'type':"SIGNAL"
+reg_1lep3_5jwin1bex0fjex0Tex1Lin0Hex1Vin = {
+    'name':"HTX_c1lep3_5jwin1bex0fjex0Tex1Lin0Hex1Vin",
+    'legend': "1l, 3-5j, 1b, 0fj, 0h, #geq1v, 0t_{h}, #geq1t_{l}",
+    'binning':"600,800,1000,1400,1600,1800,3000",
+    'binning_recoVLQ0_m':"600,700,800,900,1000,1100,1200,1300,1400,1500,1600,1700,1800,1900,2000,2200,3000",
+    'type':"VALIDATION"
 }
-reg_1lep6jin3bin1fjin1VLTin1Hin = {
-    'name':"HTX_c1lep6jin3bin1fjin1VLTin1Hin",
-    'legend': "#splitline{1l, #geq6j, #geq3b, #geq1fj}{#geq1h, #geq1(t_{l}+t_{h}+v)}",
-    'binning':"600,700,800,900,1000,1200,1400,1600,1800,3000",
-    'binning_recoVLQ0_m':"600,700,800,900,1000,1100,1200,1300,1400,1500,1600,1700,1800,1900,2000,2200,3000",#,3500,4000,4500,5000",
-    'type':"SIGNAL"
+reg_1lep3_5jwin1bex1fjin1LTin0Hex0Vex = {
+    'name':"HTX_c1lep3_5jwin1bex1fjin1LTin0Hex0Vex",
+    'legend': "1l, 3-5j, 1b, #geq1fj, 0h, 0v, #geq1t_{h}+t_{l}",
+    'binning':"600,800,1000,1400,1600,1800,3000",
+    'binning_recoVLQ0_m':"600,700,800,900,1000,1100,1200,1300,1400,1500,1600,1700,1800,1900,2000,2200,3000",
+    'type':"VALIDATION"
 }
-reg_1lep3_5jwin1_2bwin0fjex0Tex0Hex1Vin = {
-    'name':"HTX_c1lep3_5jwin1_2bwin0fjex0Tex0Hex1Vin",
-    'legend': "#splitline{1l, 3-5j, 1-2b, 0fj}{0h, #geq1v, 0t_{h}}",
-    'binning':"600,700,800,900,1000,1200,1400,1600,1800,3000",
-    'binning_recoVLQ0_m':"600,700,800,900,1000,1200,1400,1600,2000,2500,3000,3500,4000,4500,5000",
+reg_1lep3_5jwin1bex1fjin1Tin0Lex0Hex1Vin = {
+    'name':"HTX_c1lep3_5jwin1bex1fjin1Tin0Lex0Hex1Vin",
+    'legend': "1l, 3-5j, 1b, #geq1fj, 0h, #geq1v, #geq1t_{h}, 0t_{l}",
+    'binning':"600,800,1000,1400,1600,1800,3000",
+    'binning_recoVLQ0_m':"600,700,800,900,1000,1100,1200,1300,1400,1500,1600,1700,1800,1900,2000,2200,3000",
     'type':"VALIDATION"
 }
-reg_1lep3_5jwin1_2bwin1fjin1Tin0Hex0Vex = {
-    'name':"HTX_c1lep3_5jwin1_2bwin1fjin1Tin0Hex0Vex",
-    'legend': "#splitline{1l, 3-5j, 1-2b, #geq1fj}{0h, 0v, #geq1t_{h}}",
-    'binning':"600,700,800,900,1000,1200,1400,1600,1800,3000",
-    'binning_recoVLQ0_m':"600,700,800,900,1000,1200,1400,1600,2000,2500,3000,3500,4000,4500,5000",
+reg_1lep3_5jwin2bex0fjex0Tex0Lex0Hex1Vin = {
+    'name':"HTX_c1lep3_5jwin2bex0fjex0Tex0Lex0Hex1Vin",
+    'legend': "1l, 3-5j, 2b, 0fj, 0h, #geq1v, 0t_{h}, 0t_{l}",
+    'binning':"600,800,1000,1400,1600,1800,3000",
+    'binning_recoVLQ0_m':"600,700,800,900,1000,1100,1200,1300,1400,1500,1600,1700,1800,1900,2000,2200,3000",
     'type':"VALIDATION"
 }
-reg_1lep3_5jwin1_2bwin0fjex0Tex1Lin0Hex1Vin = {
-    'name':"HTX_c1lep3_5jwin1_2bwin0fjex0Tex1Lin0Hex1Vin",
-    'legend': "#splitline{1l, 3-5j, 1-2b, 0fj}{0h, #geq1v, 0t_{h}, #geq1t_{l}}",
-    'binning':"600,700,800,900,1000,1200,1400,1600,1800,3000",
-    'binning_recoVLQ0_m':"600,700,800,900,1000,1200,1400,1600,2000,2500,3000,3500,4000,4500,5000",
+reg_1lep3_5jwin2bex0fjex0Tex1Lin0Hex1Vin = {
+    'name':"HTX_c1lep3_5jwin2bex0fjex0Tex1Lin0Hex1Vin",
+    'legend': "1l, 3-5j, 2b, 0fj, 0h, #geq1v, 0t_{h}, #geq1t_{l}",
+    'binning':"600,800,1000,1400,1600,1800,3000",
+    'binning_recoVLQ0_m':"600,700,800,900,1000,1100,1200,1300,1400,1500,1600,1700,1800,1900,2000,2200,3000",
     'type':"VALIDATION"
 }
-reg_1lep3_5jwin1_2bwin1fjin1Tin0Lex0Hex1Vin = {
-    'name':"HTX_c1lep3_5jwin1_2bwin1fjin1Tin0Lex0Hex1Vin",
-    'legend': "#splitline{1l, 3-5j, 1-2b, #geq1fj}{0h, #geq1v, #geq1t_{h}, #geq0t_{l}}",
+reg_1lep3_5jwin2bex1fjin1LTin0Hex0Vex = {
+    'name':"HTX_c1lep3_5jwin2bex1fjin1LTin0Hex0Vex",
+    'legend': "1l, 3-5j, 2b, #geq1fj, 0h, 0v, #geq1t_{h}+t_{l}",
+    'binning':"600,800,1000,1400,1600,1800,3000",
+    'binning_recoVLQ0_m':"600,700,800,900,1000,1100,1200,1300,1400,1500,1600,1700,1800,1900,2000,2200,3000",
+    'type':"VALIDATION"
+}
+reg_1lep3_5jwin2bex1fjin1Tin0Lex0Hex1Vin = {
+    'name':"HTX_c1lep3_5jwin2bex1fjin1Tin0Lex0Hex1Vin",
+    'legend': "1l, 3-5j, 2b, #geq1fj, 0h, #geq1v, #geq1t_{h}, 0t_{l}",
+    'binning':"600,800,1000,1400,1600,1800,3000",
+    'binning_recoVLQ0_m':"600,700,800,900,1000,1100,1200,1300,1400,1500,1600,1700,1800,1900,2000,2200,3000",
+    'type':"VALIDATION"
+}
+reg_1lep3_5jwin3bex0fjex0Tex0Lex1Hin0Vex = {
+    'name':"HTX_c1lep3_5jwin3bex0fjex0Tex0Lex1Hin0Vex",
+    'legend': "1l, 3-5j, 3b, 0fj, #geq1h, 0v, 0t_{h}, 0t_{l}",
+    'binning':"600,800,1000,1400,1600,1800,3000",
+    'binning_recoVLQ0_m':"600,700,800,900,1000,1100,1200,1300,1400,1500,1600,1700,1800,1900,2000,2200,3000",
+    'type':"VALIDATION"
+}
+reg_1lep3_5jwin3bex0fjex0Tex1Lin1Hin0Vex = {
+    'name':"HTX_c1lep3_5jwin3bex0fjex0Tex1Lin1Hin0Vex",
+    'legend': "1l, 3-5j, 3b, 0fj, #geq1h, 0v, 0t_{h}, #geq1t_{l}",
+    'binning':"600,800,1000,1400,1600,1800,3000",
+    'binning_recoVLQ0_m':"600,700,800,900,1000,1100,1200,1300,1400,1500,1600,1700,1800,1900,2000,2200,3000",
+    'type':"VALIDATION"
+}
+reg_1lep3_5jwin3bex1fjin1Tin0Lex1Hin0Vex = {
+    'name':"HTX_c1lep3_5jwin3bex1fjin1Tin0Lex1Hin0Vex",
+    'legend': "1l, 3-5j, 3b, #geq1fj, #geq1h, 0v, #geq1t_{h}, 0t_{l}",
+    'binning':"600,800,1000,1400,1600,1800,3000",
+    'binning_recoVLQ0_m':"600,700,800,900,1000,1100,1200,1300,1400,1500,1600,1700,1800,1900,2000,2200,3000",
+    'type':"VALIDATION"
+}
+reg_1lep3_5jwin3bex1fjin1VLTin0Hex = {
+    'name':"HTX_c1lep3_5jwin3bex1fjin1VLTin0Hex",
+    'legend': "1l, 3-5j, 3b, #geq1fj, 0h, #geq1v+t_{l}+t_{h}",
+    'binning':"600,800,1000,1400,1600,1800,3000",
+    'binning_recoVLQ0_m':"600,700,800,900,1000,1100,1200,1300,1400,1500,1600,1700,1800,1900,2000,2200,3000",
+    'type':"VALIDATION"
+}
+reg_1lep3_5jwin4bin0fjex0Tex0Lex1Hin0Vex = {
+    'name':"HTX_c1lep3_5jwin4bin0fjex0Tex0Lex1Hin0Vex",
+    'legend': "1l, 3-5j, #geq4b, 0fj, #geq1h, 0v, 0t_{h}, 0t_{l}",
+    'binning':"600,800,1000,1400,1600,1800,3000",
+    'binning_recoVLQ0_m':"600,700,800,900,1000,1100,1200,1300,1400,1500,1600,1700,1800,1900,2000,2200,3000",
+    'type':"VALIDATION"
+}
+reg_1lep3_5jwin4bin0fjex0Tex1Lin1Hin0Vex = {
+    'name':"HTX_c1lep3_5jwin4bin0fjex0Tex1Lin1Hin0Vex",
+    'legend': "1l, 3-5j, #geq4b, 0fj, #geq1h, 0v, 0t_{h}, #geq1t_{l}",
+    'binning':"600,800,1000,1400,1600,1800,3000",
+    'binning_recoVLQ0_m':"600,700,800,900,1000,1100,1200,1300,1400,1500,1600,1700,1800,1900,2000,2200,3000",
+    'type':"VALIDATION"
+}
+reg_1lep3_5jwin4bin1fjin1Tin0Lex1Hin0Vex = {
+    'name':"HTX_c1lep3_5jwin4bin1fjin1Tin0Lex1Hin0Vex",
+    'legend': "1l, 3-5j, #geq4b, #geq1fj, #geq1h, 0v, #geq1t_{h}, 0t_{l}",
+    'binning':"600,800,1000,1400,1600,1800,3000",
+    'binning_recoVLQ0_m':"600,700,800,900,1000,1100,1200,1300,1400,1500,1600,1700,1800,1900,2000,2200,3000",
+    'type':"VALIDATION"
+}
+reg_1lep3_5jwin4bin1fjin1VLTin0Hex = {
+    'name':"HTX_c1lep3_5jwin4bin1fjin1VLTin0Hex",
+    'legend': "1l, 3-5j, #geq4b, #geq1fj, 0h, #geq1v+t_{l}+t_{h}",
+    'binning':"600,800,1000,1400,1600,1800,3000",
+    'binning_recoVLQ0_m':"600,700,800,900,1000,1100,1200,1300,1400,1500,1600,1700,1800,1900,2000,2200,3000",
+    'type':"VALIDATION"
+}
+reg_1lep6jin1bex0fjex1LTex0Hex1Vin = {
+    'name':"HTX_c1lep6jin1bex0fjex1LTex0Hex1Vin",
+    'legend': "1l, #geq6j, 1b, 0fj, 0h, #geq1v, 1t_{l}+t_{h}",
+    'binning':"600,800,1000,1400,1600,1800,3000",
+    'binning_recoVLQ0_m':"600,700,800,900,1000,1100,1200,1300,1400,1500,1600,1700,1800,1900,2000,2200,3000",
+    'type':"VALIDATION"
+}
+reg_1lep6jin1bex0fjex2LTin0Hex1Vin = {
+    'name':"HTX_c1lep6jin1bex0fjex2LTin0Hex1Vin",
+    'legend': "1l, #geq6j, 1b, 0fj, 0h, #geq1v, #geq2t_{h}+t_{l}",
+    'binning':"600,800,1000,1400,1600,1800,3000",
+    'binning_recoVLQ0_m':"600,700,800,900,1000,1100,1200,1300,1400,1500,1600,1700,1800,1900,2000,2200,3000",
+    'type':"VALIDATION"
+}
+reg_1lep6jin1bex1fjin0Tex0Lex1Hin1Vin = {
+    'name':"HTX_c1lep6jin1bex1fjin0Tex0Lex1Hin1Vin",
+    'legend': "1l, #geq6j, 1b, #geq1fj, #geq1h, #geq1v, 0t_{h}, 0t_{l}",
+    'binning':"600,800,1000,1400,1600,1800,3000",
+    'binning_recoVLQ0_m':"600,700,800,900,1000,1100,1200,1300,1400,1500,1600,1700,1800,1900,2000,2200,3000",
+    'type':"VALIDATION"
+}
+reg_1lep6jin1bex1fjin2LTin1Hin0Vex = {
+    'name':"HTX_c1lep6jin1bex1fjin2LTin1Hin0Vex",
+    'legend': "1l, #geq6j, 1b, #geq1fj, #geq1h, 0v, #geq2t_{h}+t_{l}",
+    'binning':"600,800,1000,1400,1600,1800,3000",
+    'binning_recoVLQ0_m':"600,700,800,900,1000,1100,1200,1300,1400,1500,1600,1700,1800,1900,2000,2200,3000",
+    'type':"VALIDATION"
+}
+reg_1lep6jin2bex0fjex1LTex0Hex1Vin = {
+    'name':"HTX_c1lep6jin2bex0fjex1LTex0Hex1Vin",
+    'legend': "1l, #geq6j, 2b, 0fj, 0h, #geq1v, 1t_{l}+t_{h}",
+    'binning':"600,800,1000,1400,1600,1800,3000",
+    'binning_recoVLQ0_m':"600,700,800,900,1000,1100,1200,1300,1400,1500,1600,1700,1800,1900,2000,2200,3000",
+    'type':"VALIDATION"
+}
+reg_1lep6jin2bex0fjex2LTin0Hex1Vin = {
+    'name':"HTX_c1lep6jin2bex0fjex2LTin0Hex1Vin",
+    'legend': "1l, #geq6j, 2b, 0fj, 0h, #geq1v, #geq2t_{h}+t_{l}",
+    'binning':"600,800,1000,1400,1600,1800,3000",
+    'binning_recoVLQ0_m':"600,700,800,900,1000,1100,1200,1300,1400,1500,1600,1700,1800,1900,2000,2200,3000",
+    'type':"VALIDATION"
+}
+reg_1lep6jin2bex1fjin0Tex0Lex1Hin1Vin = {
+    'name':"HTX_c1lep6jin2bex1fjin0Tex0Lex1Hin1Vin",
+    'legend': "1l, #geq6j, 2b, #geq1fj, #geq1h, #geq1v, 0t_{h}, 0t_{l}",
+    'binning':"600,800,1000,1400,1600,1800,3000",
+    'binning_recoVLQ0_m':"600,700,800,900,1000,1100,1200,1300,1400,1500,1600,1700,1800,1900,2000,2200,3000",
+    'type':"VALIDATION"
+}
+reg_1lep6jin2bex1fjin2LTin1Hin0Vex = {
+    'name':"HTX_c1lep6jin2bex1fjin2LTin1Hin0Vex",
+    'legend': "1l, #geq6j, 2b, #geq1fj, #geq1h, 0v, #geq2t_{h}+t_{l}",
+    'binning':"600,800,1000,1400,1600,1800,3000",
+    'binning_recoVLQ0_m':"600,700,800,900,1000,1100,1200,1300,1400,1500,1600,1700,1800,1900,2000,2200,3000",
+    'type':"VALIDATION"
+}
+reg_1lep6jin3bex0fjex1VLTex1Hin = {
+    'name':"HTX_c1lep6jin3bex0fjex1VLTex1Hin",
+    'legend': "1l, #geq6j, 3b, 0fj, #geq1h, 1v+t_{l}+t_{h}",
+    'binning':"600,800,1000,1400,1600,1800,3000",
+    'binning_recoVLQ0_m':"600,700,800,900,1000,1100,1200,1300,1400,1500,1600,1700,1800,1900,2000,2200,3000",
+    'type':"VALIDATION"
+}
+reg_1lep6jin3bex0fjex2VLTin1Hin = {
+    'name':"HTX_c1lep6jin3bex0fjex2VLTin1Hin",
+    'legend': "1l, #geq6j, 3b, 0fj, #geq1h, #geq2v+t_{l}+t_{h}",
+    'binning':"600,800,1000,1400,1600,1800,3000",
+    'binning_recoVLQ0_m':"600,700,800,900,1000,1100,1200,1300,1400,1500,1600,1700,1800,1900,2000,2200,3000",
+    'type':"VALIDATION"
+}
+reg_1lep6jin3bex1fjin1VLTex0Hex = {
+    'name':"HTX_c1lep6jin3bex1fjin1VLTex0Hex",
+    'legend': "1l, #geq6j, 3b, #geq1fj, 0h, 1v+t_{l}+t_{h}",
+    'binning':"600,800,1000,1400,1600,1800,3000",
+    'binning_recoVLQ0_m':"600,700,800,900,1000,1100,1200,1300,1400,1500,1600,1700,1800,1900,2000,2200,3000",
+    'type':"VALIDATION"
+}
+reg_1lep6jin3bex1fjin2VLTin0Hex = {
+    'name':"HTX_c1lep6jin3bex1fjin2VLTin0Hex",
+    'legend': "1l, #geq6j, 3b, #geq1fj, 0h, #geq2v+t_{l}+t_{h}",
+    'binning':"600,800,1000,1400,1600,1800,3000",
+    'binning_recoVLQ0_m':"600,700,800,900,1000,1100,1200,1300,1400,1500,1600,1700,1800,1900,2000,2200,3000",
+    'type':"VALIDATION"
+}
+reg_1lep6jin4bin0fjex1VLTex1Hin = {
+    'name':"HTX_c1lep6jin4bin0fjex1VLTex1Hin",
+    'legend': "1l, #geq6j, #geq4b, 0fj, #geq1h, 1v+t_{l}+t_{h}",
+    'binning':"600,800,1000,1400,1600,1800,3000",
+    'binning_recoVLQ0_m':"600,700,800,900,1000,1100,1200,1300,1400,1500,1600,1700,1800,1900,2000,2200,3000",
+    'type':"VALIDATION"
+}
+reg_1lep6jin4bin0fjex2VLTin1Hin = {
+    'name':"HTX_c1lep6jin4bin0fjex2VLTin1Hin",
+    'legend': "1l, #geq6j, #geq4b, 0fj, #geq1h, #geq2v+t_{l}+t_{h}",
+    'binning':"600,800,1000,1400,1600,1800,3000",
+    'binning_recoVLQ0_m':"600,700,800,900,1000,1100,1200,1300,1400,1500,1600,1700,1800,1900,2000,2200,3000",
+    'type':"VALIDATION"
+}
+reg_1lep6jin4bin1fjin1VLTex0Hex = {
+    'name':"HTX_c1lep6jin4bin1fjin1VLTex0Hex",
+    'legend': "1l, #geq6j, #geq4b, #geq1fj, 0h, 1v+t_{l}+t_{h}",
+    'binning':"600,800,1000,1400,1600,1800,3000",
+    'binning_recoVLQ0_m':"600,700,800,900,1000,1100,1200,1300,1400,1500,1600,1700,1800,1900,2000,2200,3000",
+    'type':"VALIDATION"
+}
+reg_1lep6jin4bin1fjin2VLTin0Hex = {
+    'name':"HTX_c1lep6jin4bin1fjin2VLTin0Hex",
+    'legend': "1l, #geq6j, #geq4b, #geq1fj, 0h, #geq2v+t_{l}+t_{h}",
+    'binning':"600,800,1000,1400,1600,1800,3000",
+    'binning_recoVLQ0_m':"600,700,800,900,1000,1100,1200,1300,1400,1500,1600,1700,1800,1900,2000,2200,3000",
+    'type':"VALIDATION"
+}
+
+#
+#
+# Preselection regions
+#
+#
+
+reg_1lep3_5jwin1bin = {
+    'name':"HTX_c1lep3_5jwin1bin",
+    'legend': "3-5j, #geq1b",
     'binning':"600,700,800,900,1000,1200,1400,1600,1800,3000",
-    'binning_recoVLQ0_m':"600,700,800,900,1000,1200,1400,1600,2000,2500,3000,3500,4000,4500,5000",
+    'binning_recoVLQ0_m':"600,700,800,900,1000,1100,1200,1300,1400,1500,1600,1700,1800,1900,2000,2200,3000",
     'type':"VALIDATION"
+    # 'type':"SIGNAL" # TEMP to make TRExF work with only presel regions
 }
-reg_1lep3_5jwin3bin0fjex0Tex1Lin1Hin0Vex = {
-    'name':"HTX_c1lep3_5jwin3bin0fjex0Tex1Lin1Hin0Vex",
-    'legend': "#splitline{1l, 3-5j, #geq3b, 0fj}{#geq1h, 0v, 0t_{h}, #geq1t_{l}}",
+reg_1lep3_5jwin2bin = {
+  'name':"HTX_c1lep3_5jwin2bin",
+    'legend': "3-5j, #geq2b",
     'binning':"600,700,800,900,1000,1200,1400,1600,1800,3000",
-    'binning_recoVLQ0_m':"600,700,800,900,1000,1200,1400,1600,2000,2500,3000,3500,4000,4500,5000",
+    'binning_recoVLQ0_m':"600,700,800,900,1000,1100,1200,1300,1400,1500,1600,1700,1800,1900,2000,2200,3000",
     'type':"VALIDATION"
 }
-reg_1lep3_5jwin3bin1fjin1Tin0Lex0Hex0Vex = {
-    'name':"HTX_c1lep3_5jwin3bin1fjin1Tin0Lex0Hex0Vex",
-    'legend': "#splitline{1l, 3-5j, #geq3b, #geq1fj}{0h, 0v, #geq1t_{h}, 0t_{l}}",
+reg_1lep3_5jwin3bin = {
+  'name':"HTX_c1lep3_5jwin3bin",
+    'legend': "3-5j, #geq3b",
     'binning':"600,700,800,900,1000,1200,1400,1600,1800,3000",
-    'binning_recoVLQ0_m':"0,100,200,300,400,500,600,700,800,900,1000,1200,1400,1600,2000,2500,3000,3500,4000,4500,5000",
+    'binning_recoVLQ0_m':"600,700,800,900,1000,1100,1200,1300,1400,1500,1600,1700,1800,1900,2000,2200,3000",
     'type':"VALIDATION"
 }
-reg_1lep6jin2bex0fjex2VTin0Hex = {
-    'name':"HTX_c1lep6jin2bex0fjex2VTin0Hex",
-    'legend': "#splitline{1l, #geq6j, 2b, 0fj}{0h, #geq2(v+t_{h})}",
+reg_1lep3jin1bin = {
+    'name':"HTX_c1lep3jin1bin",
+    'legend': "#geq3j, #geq1b",
     'binning':"600,700,800,900,1000,1200,1400,1600,1800,3000",
-    'binning_recoVLQ0_m':"0,100,200,300,400,500,600,700,800,900,1000,1200,1400,1600,2000,2500,3000,3500,4000,4500,5000",
+    'binning_recoVLQ0_m':"600,700,800,900,1000,1100,1200,1300,1400,1500,1600,1700,1800,1900,2000,2200,3000",
     'type':"VALIDATION"
 }
-reg_1lep6jin2bex1fjin1Tex0Hex0Vex = {
-    'name':"HTX_c1lep6jin2bex1fjin1Tex0Hex0Vex",
-    'legend': "#splitline{1l, #geq6j, 2b, #geq1fj}{0h, 0v, 1t_{h}}",
+reg_1lep3jin2bin = {
+    'name':"HTX_c1lep3jin2bin",
+    'legend': "#geq3j, #geq2b",
     'binning':"600,700,800,900,1000,1200,1400,1600,1800,3000",
-    'binning_recoVLQ0_m':"0,100,200,300,400,500,600,700,800,900,1000,1200,1400,1600,2000,2500,3000,3500,4000,4500,5000",
+    'binning_recoVLQ0_m':"600,700,800,900,1000,1100,1200,1300,1400,1500,1600,1700,1800,1900,2000,2200,3000",
     'type':"VALIDATION"
 }
-reg_1lep6jin2bex0fjex1LTin0Hex1Vin = {
-    'name':"HTX_c1lep6jin2bex0fjex1LTin0Hex1Vin",
-    'legend': "#splitline{1l, #geq6j, 2b, 0fj}{0h, #geq1v, #geq1(t_{l}+t_{h})}",
+reg_1lep3jin3bin = {
+    'name':"HTX_c1lep3jin3bin",
+    'legend': "#geq3j, #geq3b",
     'binning':"600,700,800,900,1000,1200,1400,1600,1800,3000",
-    'binning_recoVLQ0_m':"0,100,200,300,400,500,600,700,800,900,1000,1200,1400,1600,2000,2500,3000,3500,4000,4500,5000",
+    'binning_recoVLQ0_m':"600,700,800,900,1000,1100,1200,1300,1400,1500,1600,1700,1800,1900,2000,2200,3000",
     'type':"VALIDATION"
 }
-reg_1lep6jin2bex1fjin1LTin0Hex0Vex = {
-    'name':"HTX_c1lep6jin2bex1fjin1LTin0Hex0Vex",
-    'legend': "#splitline{1l, #geq6j, 2b, #geq1fj}{0h, 0v, #geq1(t_{l}+t_{h})}",
+reg_1lep5jin1bin = {
+    'name':"HTX_c1lep5jin1bin",
+    'legend': "#geq5j, #geq1b",
     'binning':"600,700,800,900,1000,1200,1400,1600,1800,3000",
-    'binning_recoVLQ0_m':"0,100,200,300,400,500,600,700,800,900,1000,1200,1400,1600,2000,2500,3000,3500,4000,4500,5000",
+    'binning_recoVLQ0_m':"600,700,800,900,1000,1100,1200,1300,1400,1500,1600,1700,1800,1900,2000,2200,3000",
     'type':"VALIDATION"
 }
-reg_1lep6jin3bin0fjex1VTin1Hin = {
-    'name':"HTX_c1lep6jin3bin0fjex1VTin1Hin",
-    'legend': "#splitline{1l, #geq6j, #geq3b, 0fj}{#geq1h, #geq1(v+t_{h})}",
+reg_1lep5jin2bin = {
+    'name':"HTX_c1lep5jin2bin",
+    'legend': "#geq5j, #geq2b",
     'binning':"600,700,800,900,1000,1200,1400,1600,1800,3000",
-    'binning_recoVLQ0_m':"0,100,200,300,400,500,600,700,800,900,1000,1200,1400,1600,2000,2500,3000,3500,4000,4500,5000",
+    'binning_recoVLQ0_m':"600,700,800,900,1000,1100,1200,1300,1400,1500,1600,1700,1800,1900,2000,2200,3000",
     'type':"VALIDATION"
 }
-reg_1lep6jin3bin1fjin1VTin0Hex = {
-    'name':"HTX_c1lep6jin3bin1fjin1VTin0Hex",
-    'legend': "#splitline{1l, #geq6j, #geq3b, #geq1fj}{0h, #geq1(v+t_{h})}",
+reg_1lep5jin3bin = {
+    'name':"HTX_c1lep5jin3bin",
+    'legend': "#geq5j, #geq3b",
     'binning':"600,700,800,900,1000,1200,1400,1600,1800,3000",
-    'binning_recoVLQ0_m':"0,100,200,300,400,500,600,700,800,900,1000,1200,1400,1600,2000,2500,3000,3500,4000,4500,5000",
+    'binning_recoVLQ0_m':"600,700,800,900,1000,1100,1200,1300,1400,1500,1600,1700,1800,1900,2000,2200,3000",
     'type':"VALIDATION"
 }
-reg_1lep6jin3bin0fjex0Tex1Lin1Hin0Vex = {
-    'name':"HTX_c1lep6jin3bin0fjex0Tex1Lin1Hin0Vex",
-    'legend': "#splitline{1l, #geq6j, #geq3b, 0fj}{#geq1h, 0v, 0t_{h}, #geq1t_{l}}",
+reg_1lep6jin1bin = {
+    'name':"HTX_c1lep6jin1bin",
+    'legend': "#geq6j, #geq1b",
     'binning':"600,700,800,900,1000,1200,1400,1600,1800,3000",
-    'binning_recoVLQ0_m':"0,100,200,300,400,500,600,700,800,900,1000,1200,1400,1600,2000,2500,3000,3500,4000,4500,5000",
+    'binning_recoVLQ0_m':"600,700,800,900,1000,1100,1200,1300,1400,1500,1600,1700,1800,1900,2000,2200,3000",
     'type':"VALIDATION"
 }
-reg_1lep6jin3bin1fjin0Tex1Lin0Hex0Vex = {
-    'name':"HTX_c1lep6jin3bin1fjin0Tex1Lin0Hex0Vex",
-    'legend': "#splitline{1l, #geq6j, #geq3b, #geq1fj}{0h, 0v, 0t_{h}, #geq1t_{l}}",
+reg_1lep6jin2bin = {
+    'name':"HTX_c1lep6jin2bin",
+    'legend': "#geq6j, #geq2b",
     'binning':"600,700,800,900,1000,1200,1400,1600,1800,3000",
-    'binning_recoVLQ0_m':"0,100,200,300,400,500,600,700,800,900,1000,1200,1400,1600,2000,2500,3000,3500,4000,4500,5000",
+    'binning_recoVLQ0_m':"600,700,800,900,1000,1100,1200,1300,1400,1500,1600,1700,1800,1900,2000,2200,3000",
     'type':"VALIDATION"
 }
-reg_1lep6jin3bin0fjex1VLTin1Hin = {
-    'name':"HTX_c1lep6jin3bin0fjex1VLTin1Hin",
-    'legend': "#splitline{1l, #geq6j, #geq3b, 0fj}{#geq1h, #geq1(v+t_{l}+t_{h})}",
+reg_1lep6jin3bin = {
+    'name':"HTX_c1lep6jin3bin",
+    'legend': "#geq6j, #geq3b",
     'binning':"600,700,800,900,1000,1200,1400,1600,1800,3000",
-    'binning_recoVLQ0_m':"0,100,200,300,400,500,600,700,800,900,1000,1200,1400,1600,2000,2500,3000,3500,4000,4500,5000",
+    'binning_recoVLQ0_m':"600,700,800,900,1000,1100,1200,1300,1400,1500,1600,1700,1800,1900,2000,2200,3000",
     'type':"VALIDATION"
 }
-reg_1lep6jin3bin1fjin1VLTin0Hex = {
-    'name':"HTX_c1lep6jin3bin1fjin1VLTin0Hex",
-    'legend': "#splitline{1l, #geq6j, #geq3b, #geq1fj}{#geq1(v+t_{l}+t_{h})}",
+reg_all = {
+    'name':"HTX_call",
+    'legend': "No selection",
     'binning':"600,700,800,900,1000,1200,1400,1600,1800,3000",
-    'binning_recoVLQ0_m':"0,100,200,300,400,500,600,700,800,900,1000,1200,1400,1600,2000,2500,3000,3500,4000,4500,5000",
+    'binning_recoVLQ0_m':"600,700,800,900,1000,1100,1200,1300,1400,1500,1600,1700,1800,1900,2000,2200,3000",
     'type':"VALIDATION"
 }
 
 fit_regions_1l = [
 
+    reg_1lep3_5jwin1bex1fjin0Tex1Lin0Hex1Vin,	
+    reg_1lep3_5jwin2bex1fjin0Tex1Lin0Hex1Vin,	
+    reg_1lep3_5jwin1bex1fjin0LTex0Hex1Vin,	
+    reg_1lep3_5jwin2bex1fjin0LTex0Hex1Vin,	
+    reg_1lep3_5jwin3bex1fjin0Tex1Lin1Hin0Vex,	
+    reg_1lep3_5jwin4bin1fjin0Tex1Lin1Hin0Vex,	
+    reg_1lep3_5jwin3bex1fjin0LTex1Hin0Vex,	
+    reg_1lep3_5jwin4bin1fjin0LTex1Hin0Vex,	
+    
+    reg_1lep6jin1bex1fjin1Lex0Tex0Hex1Vin,	
+    reg_1lep6jin2bex1fjin1Lex0Tex0Hex1Vin,	
+    reg_1lep6jin1bex1fjin0Lex1Tex0Hex1Vin,	
+    reg_1lep6jin2bex1fjin0Lex1Tex0Hex1Vin,	
+    reg_1lep6jin1bex1fjin2LTin0Hex1Vin,
+    reg_1lep6jin2bex1fjin2LTin0Hex1Vin,
+    reg_1lep6jin3bex1fjin0Lex1VTex1Hin,	
+    reg_1lep6jin4bin1fjin0Lex1VTex1Hin,	
+    reg_1lep6jin3bex1fjin1Lex0VTex1Hin,	
+    reg_1lep6jin4bin1fjin1Lex0VTex1Hin,	
+    reg_1lep6jin3bex1fjin2VLTin1Hin,	
+    reg_1lep6jin4bin1fjin2VLTin1Hin	
+]
 
-  #reg_1lep3_5jwin1_2bwin1fjin0Tex1Lin0Hex1Vin,	
-  reg_1lep3_5jwin1bex1fjin0Tex1Lin0Hex1Vin,	
-  reg_1lep3_5jwin2bex1fjin0Tex1Lin0Hex1Vin,	
-  #reg_1lep3_5jwin1_2bwin1fjin0LTex0Hex1Vin,	
-  reg_1lep3_5jwin1bex1fjin0LTex0Hex1Vin,	
-  reg_1lep3_5jwin2bex1fjin0LTex0Hex1Vin,	
-  #reg_1lep3_5jwin3bin1fjin0Tex1Lin1Hin0Vex,	
-  reg_1lep3_5jwin3bex1fjin0Tex1Lin1Hin0Vex,	
-  reg_1lep3_5jwin4bin1fjin0Tex1Lin1Hin0Vex,	
-  #reg_1lep3_5jwin3bin1fjin0LTex1Hin0Vex,	
-  reg_1lep3_5jwin3bex1fjin0LTex1Hin0Vex,	
-  reg_1lep3_5jwin4bin1fjin0LTex1Hin0Vex,	
-
-  reg_1lep6jin1bex1fjin1Lex0Tex0Hex1Vin,	
-  reg_1lep6jin2bex1fjin1Lex0Tex0Hex1Vin,	
-  reg_1lep6jin1bex1fjin0Lex1Tex0Hex1Vin,	
-  reg_1lep6jin2bex1fjin0Lex1Tex0Hex1Vin,	
-  reg_1lep6jin1bex1fjin2LTin0Hex1Vin,
-  reg_1lep6jin2bex1fjin2LTin0Hex1Vin,
-  #reg_1lep6jin3bin1fjin0Lex1VTex1Hin,	
-  reg_1lep6jin3bex1fjin0Lex1VTex1Hin,	
-  reg_1lep6jin4bin1fjin0Lex1VTex1Hin,	
-  #reg_1lep6jin3bin1fjin1Lex0VTex1Hin,	
-  reg_1lep6jin3bex1fjin1Lex0VTex1Hin,	
-  reg_1lep6jin4bin1fjin1Lex0VTex1Hin,	
-  #reg_1lep6jin3bin1fjin2VLTin1Hin,	
-  reg_1lep6jin3bex1fjin2VLTin1Hin,	
-  reg_1lep6jin4bin1fjin2VLTin1Hin	
+validation_regions_1l = [
 
+    reg_1lep3_5jwin1bex0fjex0Tex0Lex0Hex1Vin,
+    reg_1lep3_5jwin1bex0fjex0Tex1Lin0Hex1Vin,
+    reg_1lep3_5jwin1bex1fjin1LTin0Hex0Vex,
+    reg_1lep3_5jwin1bex1fjin1Tin0Lex0Hex1Vin,
+    reg_1lep3_5jwin2bex0fjex0Tex0Lex0Hex1Vin,
+    reg_1lep3_5jwin2bex0fjex0Tex1Lin0Hex1Vin,
+    reg_1lep3_5jwin2bex1fjin1LTin0Hex0Vex,
+    reg_1lep3_5jwin2bex1fjin1Tin0Lex0Hex1Vin,
+    reg_1lep3_5jwin3bex0fjex0Tex0Lex1Hin0Vex,
+    reg_1lep3_5jwin3bex0fjex0Tex1Lin1Hin0Vex,
+    reg_1lep3_5jwin3bex1fjin1Tin0Lex1Hin0Vex,
+    reg_1lep3_5jwin3bex1fjin1VLTin0Hex,
+    reg_1lep3_5jwin4bin0fjex0Tex0Lex1Hin0Vex,
+    reg_1lep3_5jwin4bin0fjex0Tex1Lin1Hin0Vex,
+    reg_1lep3_5jwin4bin1fjin1Tin0Lex1Hin0Vex,
+    reg_1lep3_5jwin4bin1fjin1VLTin0Hex,
+    
+    reg_1lep6jin1bex0fjex1LTex0Hex1Vin,
+    reg_1lep6jin1bex0fjex2LTin0Hex1Vin,
+    reg_1lep6jin1bex1fjin0Tex0Lex1Hin1Vin,
+    reg_1lep6jin1bex1fjin2LTin1Hin0Vex,
+    reg_1lep6jin2bex0fjex1LTex0Hex1Vin,
+    reg_1lep6jin2bex0fjex2LTin0Hex1Vin,
+    reg_1lep6jin2bex1fjin0Tex0Lex1Hin1Vin,
+    reg_1lep6jin2bex1fjin2LTin1Hin0Vex,
+    reg_1lep6jin3bex0fjex1VLTex1Hin,
+    reg_1lep6jin3bex0fjex2VLTin1Hin,
+    reg_1lep6jin3bex1fjin1VLTex0Hex,
+    reg_1lep6jin3bex1fjin2VLTin0Hex,
+    reg_1lep6jin4bin0fjex1VLTex1Hin,
+    reg_1lep6jin4bin0fjex2VLTin1Hin,
+    reg_1lep6jin4bin1fjin1VLTex0Hex,
+    reg_1lep6jin4bin1fjin2VLTin0Hex
 ]
 
-#fit_regions_1l = [
-# reg_1lep3_5jwin1_2bwin1fjin0Tex0Hex1Vin,
-#reg_1lep3_5jwin1_2bwin1fjin0Tex1Lin0Hex1Vin,
-#reg_1lep3_5jwin3bin1fjin0Tex1Lin1Hin0Vex,
-# reg_1lep6jin2bex1fjin2VTin0Hex,
-#reg_1lep6jin2bex1fjin1LTin0Hex1Vin,
-#reg_1lep6jin3bin1fjin1VTin1Hin
-# reg_1lep6jin3bin1fjin0Tex1Lin1Hin0Vex
-# reg_1lep6jin3bin1fjin1VLTin1Hin
-#]
+preselection_regions_1l = [
 
-validation_regions_1l = [
-# reg_1lep3_5jwin1_2bwin0fjex0Tex0Hex1Vin,
-# reg_1lep3_5jwin1_2bwin1fjin1Tin0Hex0Vex,
-reg_1lep3_5jwin1_2bwin0fjex0Tex1Lin0Hex1Vin,
-reg_1lep3_5jwin1_2bwin1fjin1Tin0Lex0Hex1Vin,
-reg_1lep3_5jwin3bin0fjex0Tex1Lin1Hin0Vex,
-reg_1lep3_5jwin3bin1fjin1Tin0Lex0Hex0Vex,
-# reg_1lep6jin2bex0fjex2VTin0Hex,
-# reg_1lep6jin2bex1fjin1Tex0Hex0Vex,
-reg_1lep6jin2bex0fjex1LTin0Hex1Vin,
-reg_1lep6jin2bex1fjin1LTin0Hex0Vex,
-reg_1lep6jin3bin0fjex1VTin1Hin,
-reg_1lep6jin3bin1fjin1VTin0Hex,
-# reg_1lep6jin3bin0fjex0Tex1Lin1Hin0Vex,
-# reg_1lep6jin3bin1fjin0Tex1Lin0Hex0Vex
-# reg_1lep6jin3bin0fjex1VLTin1Hin,
-# reg_1lep6jin3bin1fjin1VLTin0Hex
+    reg_1lep3_5jwin1bin,
+    reg_1lep3_5jwin2bin,
+    reg_1lep3_5jwin3bin,
+    reg_1lep3jin1bin,
+    reg_1lep3jin2bin,
+    reg_1lep3jin3bin,
+    reg_1lep5jin1bin,
+    reg_1lep5jin2bin,
+    reg_1lep5jin3bin,
+    reg_1lep6jin1bin,
+    reg_1lep6jin2bin,
+    reg_1lep6jin3bin,
+    reg_all
 ]
 
 all_regions_1l =  []
 all_regions_1l += fit_regions_1l
 all_regions_1l += validation_regions_1l
+all_regions_1l += preselection_regions_1l
-- 
GitLab


From de2ac04bdbca66c9b135470ee7396f8906904c0a Mon Sep 17 00:00:00 2001
From: Tal Roelof Van Daalen <tal.van.daalen@cern.ch>
Date: Wed, 8 Jan 2020 17:15:45 +0100
Subject: [PATCH 2/3] Prepared for merge with master

---
 Root/VLQ_AnalysisTools.cxx      |   5 +-
 Root/VLQ_Analysis_Data2015.cxx  |  28 ++++++-
 Root/VLQ_ResonanceMaker.cxx     |  20 ++++-
 Root/VLQ_Selector.cxx           |   8 +-
 python/MakeRegionsDictionary.py | 125 ++++++++++++++++++++++++++++++++
 5 files changed, 174 insertions(+), 12 deletions(-)
 create mode 100644 python/MakeRegionsDictionary.py

diff --git a/Root/VLQ_AnalysisTools.cxx b/Root/VLQ_AnalysisTools.cxx
index 2822946..9c97f33 100644
--- a/Root/VLQ_AnalysisTools.cxx
+++ b/Root/VLQ_AnalysisTools.cxx
@@ -518,10 +518,7 @@ bool VLQ_AnalysisTools::GetObjectVectors(){
 	isTop = isTop && ( obj -> Pt() < 800 ? m_ntupData -> d_rcjets_nconsts -> at(iRCJet) >= 2 : m_ntupData -> d_rcjets_nconsts -> at(iRCJet) >= 1);
       }
       else{
-	isTop = isTop && ( m_ntupData -> d_rcjets_nconsts -> at(iRCJet) == 1 ? obj -> Pt() > 700 :
-			   m_ntupData -> d_rcjets_nconsts -> at(iRCJet) == 2 ? obj -> Pt() > 500 :
-			   m_ntupData -> d_rcjets_nconsts -> at(iRCJet) == 3 ? obj -> Pt() > 450 :
-			   m_ntupData -> d_rcjets_nconsts -> at(iRCJet) >= 4 && obj -> Pt() > 400 );
+  isTop = isTop && ( obj -> Pt() < 700 ? m_ntupData -> d_rcjets_nconsts -> at(iRCJet) >= 2 : m_ntupData -> d_rcjets_nconsts -> at(iRCJet) >= 1);
       }
       obj -> SetMoment("isRCMTop", isTop);
       // Exclusive Higgs tagging
diff --git a/Root/VLQ_Analysis_Data2015.cxx b/Root/VLQ_Analysis_Data2015.cxx
index 3fa2da2..f6fd61f 100644
--- a/Root/VLQ_Analysis_Data2015.cxx
+++ b/Root/VLQ_Analysis_Data2015.cxx
@@ -920,6 +920,8 @@ bool VLQ_Analysis_Data2015::Begin(){
 					   DrawSyst, &(m_outData -> o_recoVLQ.at(decayType)), iTT, "m2" );
 	  m_outMngrHist -> AddStandardTH1( decayType + "_recoVLQ" + str_id + "_redm", 25, 0, 4000, ";"+decayType+" reco VLQ"+str_id+" reduced mass [GeV]"    ,  
 					   true, &(m_outData -> o_recoVLQ.at(decayType)), iTT, "redM" );
+    m_outMngrHist -> AddStandardTH1( decayType + "_recoVLQ" + str_id + "_redm2", 25, 0, 4000, ";"+decayType+" reco VLQ"+str_id+" reduced mass [GeV]"    ,  
+             true, &(m_outData -> o_recoVLQ.at(decayType)), iTT, "redM2" );
 	  m_outMngrHist -> AddStandardTH1( decayType + "_recoVLQ" + str_id + "_dR12", 0.1, 0, 6, ";"+decayType+" reco VLQ"+str_id+" #DeltaR(1,2)"    ,  
 					   DrawSyst, &(m_outData -> o_recoVLQ.at(decayType)), iTT, "dR12" );
 	  m_outMngrHist -> AddStandardTH1( decayType + "_recoVLQ" + str_id + "_dPhi12", 0.1, 0, 4, ";"+decayType+" reco VLQ"+str_id+" #Delta#phi(1,2)"    ,  
@@ -1579,13 +1581,31 @@ bool VLQ_Analysis_Data2015::Process(Long64_t entry)
     if( m_opt -> FilterType() == VLQ_Options::APPLYFILTER ){
 
       if( m_opt -> StrSampleID().find("410470.") != std::string::npos ){
-	if( ht_truth > 600 ) return false;
+  if( ht_truth > 600 ) return false;
       } else if( m_opt -> StrSampleID().find("407344.") != std::string::npos ){
-	if( ht_truth < 600 || ht_truth > 1000 ) return false;
+  if( ht_truth < 600 || ht_truth > 1000 ) return false;
       } else if( m_opt -> StrSampleID().find("407343.") != std::string::npos  ){
-	if( ht_truth < 1000 || ht_truth > 1500 ) return false;
+  if( ht_truth < 1000 || ht_truth > 1500 ) return false;
       } else if( m_opt -> StrSampleID().find("407342.") != std::string::npos ){
-	if( ht_truth < 1500 ) return false;
+  if( ht_truth < 1500 ) return false;
+      // Powheg+Herwig7
+      } else if( (m_opt -> StrSampleID().find("410557.") != std::string::npos) || (m_opt -> StrSampleID().find("410558.") != std::string::npos) ){
+  if( ht_truth > 600 ) return false;
+      } else if( m_opt -> StrSampleID().find("407356.") != std::string::npos ){
+  if( ht_truth < 600 || ht_truth > 1000 ) return false;
+      } else if( m_opt -> StrSampleID().find("407355.") != std::string::npos  ){
+  if( ht_truth < 1000 || ht_truth > 1500 ) return false;
+      } else if( m_opt -> StrSampleID().find("407354.") != std::string::npos ){
+  if( ht_truth < 1500 ) return false;
+      // aMC@NLO+Pythia8
+      } else if( (m_opt -> StrSampleID().find("410464.") != std::string::npos) || (m_opt -> StrSampleID().find("410465.") != std::string::npos) ){
+  if( ht_truth > 600 ) return false;
+      } else if( m_opt -> StrSampleID().find("407350.") != std::string::npos ){
+  if( ht_truth < 600 || ht_truth > 1000 ) return false;
+      } else if( m_opt -> StrSampleID().find("407349.") != std::string::npos  ){
+  if( ht_truth < 1000 || ht_truth > 1500 ) return false;
+      } else if( m_opt -> StrSampleID().find("407348.") != std::string::npos ){
+  if( ht_truth < 1500 ) return false;
       }
       
     }//filter
diff --git a/Root/VLQ_ResonanceMaker.cxx b/Root/VLQ_ResonanceMaker.cxx
index dd869d5..1892518 100644
--- a/Root/VLQ_ResonanceMaker.cxx
+++ b/Root/VLQ_ResonanceMaker.cxx
@@ -401,6 +401,15 @@ int VLQ_ResonanceMaker::MakeSingleVLQ( const std::string& decay ){
     recoVLQ->SetMoment("m1", res1->M());
     recoVLQ->SetMoment("m2", res2->M());
     recoVLQ->SetMoment("redM", recoVLQ->M() - res1->M() - res2->M());
+    if(decay == "Ht"){
+      recoVLQ->SetMoment("redM2", recoVLQ->M() - fabs(res1->M()-125.18) - fabs(res2->M()-172.84));
+    }
+    if(decay == "Zt"){
+      recoVLQ->SetMoment("redM2", recoVLQ->M() - fabs(res1->M()-91.1876) - fabs(res2->M()-172.84));
+    }
+    if(decay == "Wb"){
+      recoVLQ->SetMoment("redM2", recoVLQ->M() - fabs(res1->M()-80.370) - fabs(res2->M()-4.18));
+    }
 
     double fpt = (decay=="Wb") ? res2->Pt()/res1->Pt() : res1->Pt()/res2->Pt();
     recoVLQ -> SetMoment("fpT12", fpt);
@@ -513,7 +522,16 @@ int VLQ_ResonanceMaker::MakePairVLQ( const std::string& decay, const double drma
     recoVLQ->SetMoment("m1", res1->M());
     recoVLQ->SetMoment("m2", res2->M());
     recoVLQ->SetMoment("redM", recoVLQ->M() - res1->M() - res2->M());
-
+    if(decay == "Ht"){
+      recoVLQ->SetMoment("redM2", recoVLQ->M() - fabs(res1->M()-125.18) - fabs(res2->M()-172.84));
+    }
+    if(decay == "Zt"){
+      recoVLQ->SetMoment("redM2", recoVLQ->M() - fabs(res1->M()-91.1876) - fabs(res2->M()-172.84));
+    }
+    if(decay == "Wb"){
+      recoVLQ->SetMoment("redM2", recoVLQ->M() - fabs(res1->M()-80.370) - fabs(res2->M()-4.18));
+    }
+    
     double fpt = (decay=="Wb") ? res2->Pt()/res1->Pt() : res1->Pt()/res2->Pt();
     recoVLQ -> SetMoment("fpT12", fpt);
 
diff --git a/Root/VLQ_Selector.cxx b/Root/VLQ_Selector.cxx
index f557aff..385a1f0 100644
--- a/Root/VLQ_Selector.cxx
+++ b/Root/VLQ_Selector.cxx
@@ -322,9 +322,11 @@ bool VLQ_Selector::Init(){
 
     AddVLQSelection(lep_prefix+"3_5jwin-3bex-1fjin-0LTex-1Hin-0Vex", do_runop, do_syst, SINGLEVLQ);    //SR2-a
     AddVLQSelection(lep_prefix+"3_5jwin-3bex-1fjin-0Tex-1Lin-1Hin-0Vex", do_runop, do_syst, SINGLEVLQ);    //SR2-b ORIG
+    AddVLQSelection(lep_prefix+"3_5jwin-3bex-1fjin-1Tin-0Lex-1Hin-0Vex", do_runop, do_syst, SINGLEVLQ);
 
     AddVLQSelection(lep_prefix+"3_5jwin-4bin-1fjin-0LTex-1Hin-0Vex", do_runop, do_syst, SINGLEVLQ);    //SR2-a
     AddVLQSelection(lep_prefix+"3_5jwin-4bin-1fjin-0Tex-1Lin-1Hin-0Vex", do_runop, do_syst, SINGLEVLQ);    //SR2-b ORIG
+    AddVLQSelection(lep_prefix+"3_5jwin-4bin-1fjin-1Tin-0Lex-1Hin-0Vex", do_runop, do_syst, SINGLEVLQ);
 
     AddVLQSelection(lep_prefix+"6jin-1bex-1fjin-1Lex-0Tex-0Hex-1Vin", do_runop, do_syst, SINGLEVLQ);       //SR3-a 
     AddVLQSelection(lep_prefix+"6jin-1bex-1fjin-0Lex-1Tex-0Hex-1Vin", do_runop, do_syst, SINGLEVLQ);       //SR3-b 
@@ -357,12 +359,12 @@ bool VLQ_Selector::Init(){
 
       AddVLQSelection(lep_prefix+"3_5jwin-3bex-0fjex-0Tex-0Lex-1Hin-0Vex", do_runop, do_syst, SINGLEVLQ);
       AddVLQSelection(lep_prefix+"3_5jwin-3bex-0fjex-0Tex-1Lin-1Hin-0Vex", do_runop, do_syst, SINGLEVLQ);
-      AddVLQSelection(lep_prefix+"3_5jwin-3bex-1fjin-1Tin-0Lex-1Hin-0Vex", do_runop, do_syst, SINGLEVLQ); // TOO HIGH SIGNAL
+      // AddVLQSelection(lep_prefix+"3_5jwin-3bex-1fjin-1Tin-0Lex-1Hin-0Vex", do_runop, do_syst, SINGLEVLQ); // TOO HIGH SIGNAL
       AddVLQSelection(lep_prefix+"3_5jwin-3bex-1fjin-1VLTin-0Hex", do_runop, do_syst, SINGLEVLQ);
 
       AddVLQSelection(lep_prefix+"3_5jwin-4bin-0fjex-0Tex-0Lex-1Hin-0Vex", do_runop, do_syst, SINGLEVLQ);
       AddVLQSelection(lep_prefix+"3_5jwin-4bin-0fjex-0Tex-1Lin-1Hin-0Vex", do_runop, do_syst, SINGLEVLQ);
-      AddVLQSelection(lep_prefix+"3_5jwin-4bin-1fjin-1Tin-0Lex-1Hin-0Vex", do_runop, do_syst, SINGLEVLQ); // TOO HIGH SIGNAL
+      // AddVLQSelection(lep_prefix+"3_5jwin-4bin-1fjin-1Tin-0Lex-1Hin-0Vex", do_runop, do_syst, SINGLEVLQ); // TOO HIGH SIGNAL
       AddVLQSelection(lep_prefix+"3_5jwin-4bin-1fjin-1VLTin-0Hex", do_runop, do_syst, SINGLEVLQ);
 
       AddVLQSelection(lep_prefix+"6jin-1bex-0fjex-1LTex-0Hex-1Vin", do_runop, do_syst, SINGLEVLQ);
@@ -381,7 +383,7 @@ bool VLQ_Selector::Init(){
       AddVLQSelection(lep_prefix+"6jin-3bex-1fjin-2VLTin-0Hex", do_runop, do_syst, SINGLEVLQ);
 
       AddVLQSelection(lep_prefix+"6jin-4bin-0fjex-1VLTex-1Hin", do_runop, do_syst, SINGLEVLQ);
-      AddVLQSelection(lep_prefix+"6jin-4bin-0fjex-2VLTin-1Hin", do_runop, do_syst, SINGLEVLQ); // TOO HIGH SIGNAL
+      // AddVLQSelection(lep_prefix+"6jin-4bin-0fjex-2VLTin-1Hin", do_runop, do_syst, SINGLEVLQ); // TOO HIGH SIGNAL
       AddVLQSelection(lep_prefix+"6jin-4bin-1fjin-1VLTex-0Hex", do_runop, do_syst, SINGLEVLQ);
       AddVLQSelection(lep_prefix+"6jin-4bin-1fjin-2VLTin-0Hex", do_runop, do_syst, SINGLEVLQ);
     }
diff --git a/python/MakeRegionsDictionary.py b/python/MakeRegionsDictionary.py
new file mode 100644
index 0000000..9e52c8c
--- /dev/null
+++ b/python/MakeRegionsDictionary.py
@@ -0,0 +1,125 @@
+import re
+
+SR=['c1lep3_5jwin-1bex-1fjin-0LTex-0Hex-1Vin',
+'c1lep3_5jwin-1bex-1fjin-0Tex-1Lin-0Hex-1Vin',
+'c1lep3_5jwin-2bex-1fjin-0LTex-0Hex-1Vin',
+'c1lep3_5jwin-2bex-1fjin-0Tex-1Lin-0Hex-1Vin',
+'c1lep3_5jwin-3bex-1fjin-0LTex-1Hin-0Vex',
+'c1lep3_5jwin-3bex-1fjin-0Tex-1Lin-1Hin-0Vex',
+'c1lep3_5jwin-3bex-1fjin-1Tin-0Lex-1Hin-0Vex',
+'c1lep3_5jwin-4bin-1fjin-0LTex-1Hin-0Vex',
+'c1lep3_5jwin-4bin-1fjin-0Tex-1Lin-1Hin-0Vex',
+'c1lep3_5jwin-4bin-1fjin-1Tin-0Lex-1Hin-0Vex',
+'c1lep6jin-1bex-1fjin-1Lex-0Tex-0Hex-1Vin',
+'c1lep6jin-1bex-1fjin-0Lex-1Tex-0Hex-1Vin',
+'c1lep6jin-1bex-1fjin-2LTin-0Hex-1Vin',
+'c1lep6jin-2bex-1fjin-1Lex-0Tex-0Hex-1Vin',
+'c1lep6jin-2bex-1fjin-0Lex-1Tex-0Hex-1Vin',
+'c1lep6jin-2bex-1fjin-2LTin-0Hex-1Vin',
+'c1lep6jin-3bex-1fjin-1Lex-0VTex-1Hin',
+'c1lep6jin-3bex-1fjin-0Lex-1VTex-1Hin',
+'c1lep6jin-3bex-1fjin-2VLTin-1Hin',
+'c1lep6jin-4bin-1fjin-1Lex-0VTex-1Hin',
+'c1lep6jin-4bin-1fjin-0Lex-1VTex-1Hin',
+'c1lep6jin-4bin-1fjin-2VLTin-1Hin']
+
+VR=['c1lep3_5jwin-1bex-0fjex-0Tex-0Lex-0Hex-1Vin',
+'c1lep3_5jwin-1bex-0fjex-0Tex-1Lin-0Hex-1Vin',
+'c1lep3_5jwin-1bex-1fjin-1LTin-0Hex-0Vex',
+'c1lep3_5jwin-1bex-1fjin-1Tin-0Lex-0Hex-1Vin',
+'c1lep3_5jwin-2bex-0fjex-0Tex-0Lex-0Hex-1Vin',
+'c1lep3_5jwin-2bex-0fjex-0Tex-1Lin-0Hex-1Vin',
+'c1lep3_5jwin-2bex-1fjin-1LTin-0Hex-0Vex',
+'c1lep3_5jwin-2bex-1fjin-1Tin-0Lex-0Hex-1Vin',
+'c1lep3_5jwin-3bex-0fjex-0Tex-0Lex-1Hin-0Vex',
+'c1lep3_5jwin-3bex-0fjex-0Tex-1Lin-1Hin-0Vex',
+'c1lep3_5jwin-3bex-1fjin-1VLTin-0Hex',
+'c1lep3_5jwin-4bin-0fjex-0Tex-0Lex-1Hin-0Vex',
+'c1lep3_5jwin-4bin-0fjex-0Tex-1Lin-1Hin-0Vex',
+'c1lep3_5jwin-4bin-1fjin-1VLTin-0Hex',
+'c1lep6jin-1bex-0fjex-1LTex-0Hex-1Vin',
+'c1lep6jin-1bex-0fjex-2LTin-0Hex-1Vin',
+'c1lep6jin-1bex-1fjin-0Tex-0Lex-1Hin-1Vin',
+'c1lep6jin-1bex-1fjin-2LTin-1Hin-0Vex',
+'c1lep6jin-2bex-0fjex-1LTex-0Hex-1Vin',
+'c1lep6jin-2bex-0fjex-2LTin-0Hex-1Vin',
+'c1lep6jin-2bex-1fjin-0Tex-0Lex-1Hin-1Vin',
+'c1lep6jin-2bex-1fjin-2LTin-1Hin-0Vex',
+'c1lep6jin-3bex-0fjex-1VLTex-1Hin',
+'c1lep6jin-3bex-0fjex-2VLTin-1Hin',
+'c1lep6jin-3bex-1fjin-1VLTex-0Hex',
+'c1lep6jin-3bex-1fjin-2VLTin-0Hex',
+'c1lep6jin-4bin-0fjex-1VLTex-1Hin',
+'c1lep6jin-4bin-1fjin-1VLTex-0Hex',
+'c1lep6jin-4bin-1fjin-2VLTin-0Hex']
+
+def printregions(l,typ):
+  for region in l:
+    legend = ""
+    items = 0
+    if region == "call":
+      legend = "No selection"
+  
+    if '3_5jwin' in region:
+      legend+='LJ'
+      items+=1
+    if '6jin' in region:
+      legend+='HJ'
+      items+=1
+
+    if 'b' in region:
+      legend+=', '+region[region.index('b')-1]+'b'
+      items+=1
+    if 'fj' in region:
+      legend+=', '+region[region.index('fj')-1]+'fj'
+      items+=1
+
+    if 'TH' in region:
+      legend+=', '+region[region.index('TH')-1]+'h+t_{h}'
+      items+=1
+    elif 'T' in region and region[region.index('T')-1].isdigit():
+      legend+=', '+region[region.index('T')-1]+'t_{h}'
+      items+=1
+
+    if 'LT' in region and region[region.index('LT')-1].isdigit():
+      legend+=', '+region[region.index('LT')-1]+'(t_{h}+t_{l})'
+      items+=2
+    elif 'L' in region and region[region.index('L')-1].isdigit():
+      legend+=', '+region[region.index('L')-1]+'t_{l}'
+      items+=1  
+
+    if 'H' in region:
+      legend+=', '+region[region.index('H')-1]+'h'
+      items+=1
+  
+    if 'VLT' in region:
+      legend+=', '+region[region.index('VLT')-1]+'(v+t_{l}+t_{h})'
+      items+=2
+    if 'VT' in region:
+      legend+=', '+region[region.index('VT')-1]+'(v+t_{h})'
+      items+=2
+
+    if 'V' in region and region[region.index('V')-1].isdigit() and not 'v' in legend:
+      legend+=', '+region[region.index('V')-1]+'V'
+      items+=1 
+    
+    if items >= 4:
+      splitindex = [i.start() for i in re.finditer(', ',legend)][int(items/2)]+1
+      legend = '#splitline{%s}{%s}'%(legend[:splitindex],legend[splitindex+1:])
+
+    # print region
+    # print legend
+    # print ""
+
+    print "reg_"+region[1:]+" = {"
+    print "\t'name':"+'"HTX_'+region+'",'
+    # print "\t'legend': "+'"'+legend+'",'
+    print "\t'legend': "+'"#scale[0.75]{'+legend+'}",'
+    print "\t'binning':"+'"600,800,1000,1400,1600,1800,3000",'
+    print "\t'binning_recoVLQ0_m':"+'"600,700,800,900,1000,1100,1200,1300,1400,1500,1600,1700,1800,1900,2000,2200,3000",'
+    print "\t'type':"+'"%s"'%typ
+    print '}'
+
+printregions(SR,"SIGNAL")
+print "\n\n"
+printregions(VR,"SIGNAL")
\ No newline at end of file
-- 
GitLab


From 0c7f59321221d06ad28da7199adbdac26fee5a3c Mon Sep 17 00:00:00 2001
From: Tal Roelof Van Daalen <tal.van.daalen@cern.ch>
Date: Thu, 9 Jan 2020 11:43:30 +0100
Subject: [PATCH 3/3] Quick fix in MakeRegionsDictionary.py

---
 python/MakeRegionsDictionary.py | 102 ++++++++++++++++----------------
 1 file changed, 51 insertions(+), 51 deletions(-)

diff --git a/python/MakeRegionsDictionary.py b/python/MakeRegionsDictionary.py
index 9e52c8c..57eaf42 100644
--- a/python/MakeRegionsDictionary.py
+++ b/python/MakeRegionsDictionary.py
@@ -1,57 +1,57 @@
 import re
 
-SR=['c1lep3_5jwin-1bex-1fjin-0LTex-0Hex-1Vin',
-'c1lep3_5jwin-1bex-1fjin-0Tex-1Lin-0Hex-1Vin',
-'c1lep3_5jwin-2bex-1fjin-0LTex-0Hex-1Vin',
-'c1lep3_5jwin-2bex-1fjin-0Tex-1Lin-0Hex-1Vin',
-'c1lep3_5jwin-3bex-1fjin-0LTex-1Hin-0Vex',
-'c1lep3_5jwin-3bex-1fjin-0Tex-1Lin-1Hin-0Vex',
-'c1lep3_5jwin-3bex-1fjin-1Tin-0Lex-1Hin-0Vex',
-'c1lep3_5jwin-4bin-1fjin-0LTex-1Hin-0Vex',
-'c1lep3_5jwin-4bin-1fjin-0Tex-1Lin-1Hin-0Vex',
-'c1lep3_5jwin-4bin-1fjin-1Tin-0Lex-1Hin-0Vex',
-'c1lep6jin-1bex-1fjin-1Lex-0Tex-0Hex-1Vin',
-'c1lep6jin-1bex-1fjin-0Lex-1Tex-0Hex-1Vin',
-'c1lep6jin-1bex-1fjin-2LTin-0Hex-1Vin',
-'c1lep6jin-2bex-1fjin-1Lex-0Tex-0Hex-1Vin',
-'c1lep6jin-2bex-1fjin-0Lex-1Tex-0Hex-1Vin',
-'c1lep6jin-2bex-1fjin-2LTin-0Hex-1Vin',
-'c1lep6jin-3bex-1fjin-1Lex-0VTex-1Hin',
-'c1lep6jin-3bex-1fjin-0Lex-1VTex-1Hin',
-'c1lep6jin-3bex-1fjin-2VLTin-1Hin',
-'c1lep6jin-4bin-1fjin-1Lex-0VTex-1Hin',
-'c1lep6jin-4bin-1fjin-0Lex-1VTex-1Hin',
-'c1lep6jin-4bin-1fjin-2VLTin-1Hin']
+SR=['c1lep3_5jwin1bex1fjin0LTex0Hex1Vin',
+'c1lep3_5jwin1bex1fjin0Tex1Lin0Hex1Vin',
+'c1lep3_5jwin2bex1fjin0LTex0Hex1Vin',
+'c1lep3_5jwin2bex1fjin0Tex1Lin0Hex1Vin',
+'c1lep3_5jwin3bex1fjin0LTex1Hin0Vex',
+'c1lep3_5jwin3bex1fjin0Tex1Lin1Hin0Vex',
+'c1lep3_5jwin3bex1fjin1Tin0Lex1Hin0Vex',
+'c1lep3_5jwin4bin1fjin0LTex1Hin0Vex',
+'c1lep3_5jwin4bin1fjin0Tex1Lin1Hin0Vex',
+'c1lep3_5jwin4bin1fjin1Tin0Lex1Hin0Vex',
+'c1lep6jin1bex1fjin1Lex0Tex0Hex1Vin',
+'c1lep6jin1bex1fjin0Lex1Tex0Hex1Vin',
+'c1lep6jin1bex1fjin2LTin0Hex1Vin',
+'c1lep6jin2bex1fjin1Lex0Tex0Hex1Vin',
+'c1lep6jin2bex1fjin0Lex1Tex0Hex1Vin',
+'c1lep6jin2bex1fjin2LTin0Hex1Vin',
+'c1lep6jin3bex1fjin1Lex0VTex1Hin',
+'c1lep6jin3bex1fjin0Lex1VTex1Hin',
+'c1lep6jin3bex1fjin2VLTin1Hin',
+'c1lep6jin4bin1fjin1Lex0VTex1Hin',
+'c1lep6jin4bin1fjin0Lex1VTex1Hin',
+'c1lep6jin4bin1fjin2VLTin1Hin']
 
-VR=['c1lep3_5jwin-1bex-0fjex-0Tex-0Lex-0Hex-1Vin',
-'c1lep3_5jwin-1bex-0fjex-0Tex-1Lin-0Hex-1Vin',
-'c1lep3_5jwin-1bex-1fjin-1LTin-0Hex-0Vex',
-'c1lep3_5jwin-1bex-1fjin-1Tin-0Lex-0Hex-1Vin',
-'c1lep3_5jwin-2bex-0fjex-0Tex-0Lex-0Hex-1Vin',
-'c1lep3_5jwin-2bex-0fjex-0Tex-1Lin-0Hex-1Vin',
-'c1lep3_5jwin-2bex-1fjin-1LTin-0Hex-0Vex',
-'c1lep3_5jwin-2bex-1fjin-1Tin-0Lex-0Hex-1Vin',
-'c1lep3_5jwin-3bex-0fjex-0Tex-0Lex-1Hin-0Vex',
-'c1lep3_5jwin-3bex-0fjex-0Tex-1Lin-1Hin-0Vex',
-'c1lep3_5jwin-3bex-1fjin-1VLTin-0Hex',
-'c1lep3_5jwin-4bin-0fjex-0Tex-0Lex-1Hin-0Vex',
-'c1lep3_5jwin-4bin-0fjex-0Tex-1Lin-1Hin-0Vex',
-'c1lep3_5jwin-4bin-1fjin-1VLTin-0Hex',
-'c1lep6jin-1bex-0fjex-1LTex-0Hex-1Vin',
-'c1lep6jin-1bex-0fjex-2LTin-0Hex-1Vin',
-'c1lep6jin-1bex-1fjin-0Tex-0Lex-1Hin-1Vin',
-'c1lep6jin-1bex-1fjin-2LTin-1Hin-0Vex',
-'c1lep6jin-2bex-0fjex-1LTex-0Hex-1Vin',
-'c1lep6jin-2bex-0fjex-2LTin-0Hex-1Vin',
-'c1lep6jin-2bex-1fjin-0Tex-0Lex-1Hin-1Vin',
-'c1lep6jin-2bex-1fjin-2LTin-1Hin-0Vex',
-'c1lep6jin-3bex-0fjex-1VLTex-1Hin',
-'c1lep6jin-3bex-0fjex-2VLTin-1Hin',
-'c1lep6jin-3bex-1fjin-1VLTex-0Hex',
-'c1lep6jin-3bex-1fjin-2VLTin-0Hex',
-'c1lep6jin-4bin-0fjex-1VLTex-1Hin',
-'c1lep6jin-4bin-1fjin-1VLTex-0Hex',
-'c1lep6jin-4bin-1fjin-2VLTin-0Hex']
+VR=['c1lep3_5jwin1bex0fjex0Tex0Lex0Hex1Vin',
+'c1lep3_5jwin1bex0fjex0Tex1Lin0Hex1Vin',
+'c1lep3_5jwin1bex1fjin1LTin0Hex0Vex',
+'c1lep3_5jwin1bex1fjin1Tin0Lex0Hex1Vin',
+'c1lep3_5jwin2bex0fjex0Tex0Lex0Hex1Vin',
+'c1lep3_5jwin2bex0fjex0Tex1Lin0Hex1Vin',
+'c1lep3_5jwin2bex1fjin1LTin0Hex0Vex',
+'c1lep3_5jwin2bex1fjin1Tin0Lex0Hex1Vin',
+'c1lep3_5jwin3bex0fjex0Tex0Lex1Hin0Vex',
+'c1lep3_5jwin3bex0fjex0Tex1Lin1Hin0Vex',
+'c1lep3_5jwin3bex1fjin1VLTin0Hex',
+'c1lep3_5jwin4bin0fjex0Tex0Lex1Hin0Vex',
+'c1lep3_5jwin4bin0fjex0Tex1Lin1Hin0Vex',
+'c1lep3_5jwin4bin1fjin1VLTin0Hex',
+'c1lep6jin1bex0fjex1LTex0Hex1Vin',
+'c1lep6jin1bex0fjex2LTin0Hex1Vin',
+'c1lep6jin1bex1fjin0Tex0Lex1Hin1Vin',
+'c1lep6jin1bex1fjin2LTin1Hin0Vex',
+'c1lep6jin2bex0fjex1LTex0Hex1Vin',
+'c1lep6jin2bex0fjex2LTin0Hex1Vin',
+'c1lep6jin2bex1fjin0Tex0Lex1Hin1Vin',
+'c1lep6jin2bex1fjin2LTin1Hin0Vex',
+'c1lep6jin3bex0fjex1VLTex1Hin',
+'c1lep6jin3bex0fjex2VLTin1Hin',
+'c1lep6jin3bex1fjin1VLTex0Hex',
+'c1lep6jin3bex1fjin2VLTin0Hex',
+'c1lep6jin4bin0fjex1VLTex1Hin',
+'c1lep6jin4bin1fjin1VLTex0Hex',
+'c1lep6jin4bin1fjin2VLTin0Hex']
 
 def printregions(l,typ):
   for region in l:
-- 
GitLab