- Jul 01, 2019
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Julien Egli authored
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- Jun 26, 2019
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Julien Egli authored
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- Jun 21, 2019
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Julien Egli authored
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Julien Egli authored
This reverts commit 161c869e, reversing changes made to 99728a89.
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Julien Egli authored
This reverts commit c93c27bf.
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Julien Egli authored
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Julien Egli authored
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Julien Egli authored
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Julien Egli authored
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- Jun 20, 2019
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Nathan Pittet authored
Same functionality, using rising_edge instead of events, and signal instead of shared variable, the later causing problems depending on the simulator used
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Nathan Pittet authored
Adapted design so that the buffers width can be different than 32 bits until the last steps of the observation
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Nathan Pittet authored
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- Jun 12, 2019
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Julien Egli authored
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- Jun 07, 2019
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Julien Egli authored
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- May 28, 2019
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Julien Egli authored
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- May 07, 2019
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Julien Egli authored
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- May 03, 2019
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Julien Egli authored
- files were copied into the project during the project creation -> solved
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Julien Egli authored
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- Apr 18, 2019
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Julien Egli authored
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- Apr 17, 2019
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Julien Egli authored
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Julien Egli authored
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Julien Egli authored
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Julien Egli authored
- Ext simulation not fully tested
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- Apr 15, 2019
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Julien Egli authored
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Julien Egli authored
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Julien Egli authored
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- Apr 12, 2019
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Julien Egli authored
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- Apr 11, 2019
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Julien Egli authored
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Julien Egli authored
- acq_finished signal corrected
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- Apr 08, 2019
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Julien Egli authored
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Julien Egli authored
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Julien Egli authored
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Julien Egli authored
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Julien Egli authored
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Julien Egli authored
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Julien Egli authored
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Julien Egli authored
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Julien Egli authored
- removed Work directory - Corrected C&P faults in the memory map
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Julien Egli authored
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