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This is an archived project. Repository and other project resources are read-only.
John Robert Gill
wr-d3s-adc
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risc-v
dc0fe6ed
·
hdl: changed lm32 with risc-v
·
Mar 21, 2017
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evaC-StreamStart-patch
77ce62b7
·
hdl:rtl RF enc/dec enabled only if clocks locked
·
Mar 23, 2017
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devfede
1e5f62a1
·
DBG sw:rt:slave: proof that the filter gate happens always
·
Mar 28, 2017
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master
default
protected
9c0c4ae5
·
sw:rt:master: remove RF priority loop
·
Mar 28, 2017
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devfede-ut
a39b1e47
·
sw:ut: stop the D3S when the test is over
·
Mar 31, 2017
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evaG_dev
53b8865a
·
changed Trev module so that it continues producing Trev, even if a message...
·
Mar 31, 2017
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evaC-newSTDC
18eff741
·
hdl:STDC fix small bug in valid register
·
Apr 09, 2017
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tom-apr19
8444d8cf
·
d3s_phase_encoder: fixed incorrect timestamp generation (equal to 125e6) which caused
·
Apr 19, 2017
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evaG_dev_upsmpl
b5f7552e
·
[hdl] changed ise mapping options to meet constraints
·
Apr 21, 2017
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evaC-newTrevGen
817aca8f
·
hdl:testbench Added assertions for CI test.
·
Apr 27, 2017
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adam-ci
ad361647
·
hdl/testbench: add a Makefile to be run by CI
·
Apr 27, 2017
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evaC-newTrevGen-fede
59ad915f
·
SQUASH with patch that reduce TAI size from 40 to 32
·
Apr 27, 2017
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evaG_dev_upsmpl2
a8947db4
·
[hdl] future timestamp calculated in TrevGen_Module goes in to the d3s_upsample_divide
·
Apr 27, 2017
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evaC-NewUpsampler
1e74f851
·
hdl:testbench WIP with the DAC
·
Apr 28, 2017
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tom-apr26
10a45f71
·
updated submodules
·
May 03, 2017
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tom-may03
96347aaa
·
updated submodules
·
May 04, 2017
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tom-may09
922df8ba
·
wip
·
May 09, 2017
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eva-may09-hw
d25dbbc8
·
hdl:slave divide. Added chipscope and signals for debugging
·
May 09, 2017
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tom-may14
58b9a7f4
·
Merge branch 'tom-may14' of
ssh://gitlab.cern.ch:7999/ecalvo/wr-d3s-adc
into tom-may14
·
May 19, 2017
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evaG-may23
ea20d935
·
added essential iobuff that enable us to keep the same ucf for master or slave implementation
·
May 30, 2017
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