From 8befa4c7b8d679579cff9789415de0d18f5118e6 Mon Sep 17 00:00:00 2001 From: Roel Aaij <raaij@nikhef.nl> Date: Mon, 25 Apr 2016 15:16:17 +0200 Subject: [PATCH 1/3] Fix routing bit 92. --- Hlt/HltConf/python/HltConf/HltOutput.py | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) diff --git a/Hlt/HltConf/python/HltConf/HltOutput.py b/Hlt/HltConf/python/HltConf/HltOutput.py index bf851d1ce..a6b66f59a 100644 --- a/Hlt/HltConf/python/HltConf/HltOutput.py +++ b/Hlt/HltConf/python/HltConf/HltOutput.py @@ -85,8 +85,8 @@ class HltOutputConf(LHCbConfigurableUser): # (only matters if EnablelumiEventWriting = True) 'Hlt2LinesForDQ' : ['PIDD02KPiTagTurboCalib', 'PIDLambda2PPiLLTurboCalib', 'PIDDetJPsiMuMuPosTaggedTurboCalib', 'PIDDetJPsiMuMuNegTaggedTurboCalib', 'PIDLambda2PPiLLhighPTTurboCalib', 'PIDLambda2PPiLLveryhighPTTurboCalib', - 'DiMuonDetachedJPsi', 'Hlt2PIDDs2PiPhiKKNegTaggedTurboCalib', 'Hlt2PIDDs2PiPhiKKPosTaggedTurboCalib', - 'Hlt2PIDDs2PiPhiKKUnbiasedTurboCalib'], + 'DiMuonDetachedJPsi', 'PIDDs2PiPhiKKNegTaggedTurboCalib', 'PIDDs2PiPhiKKPosTaggedTurboCalib', + 'PIDDs2PiPhiKKUnbiasedTurboCalib'], '_streams' : None # Cache property } @@ -339,7 +339,7 @@ class HltOutputConf(LHCbConfigurableUser): # RB 91 for the NOBIAS stream , 91 : "HLT_PASS('Hlt2MBNoBiasDecision')" # RB 92 for online DQ on HLT2 output - , 92 : "HLT_PASS('Hlt2(%s)Decision')" % '|'.join(self.getProp("Hlt2LinesForDQ")) + , 92 : "HLT_PASS_RE('Hlt2(%s)Decision')" % '|'.join(self.getProp("Hlt2LinesForDQ")) # RB 93 for SMOG physics; reserved # RB 94 LUMI stream , 94 : self.getProp('LumiPredicate') @@ -514,7 +514,8 @@ class HltOutputConf(LHCbConfigurableUser): streamSequence.Members += [prepSequence] # Always pass the HLT1 routing bits - rbs = {k : routingBits[k] for k in routingBits.iterkeys() if k < 64} + streamBits = set(self.knownStreams().values()) + rbs = {k : routingBits[k] for k in routingBits.iterkeys() if k < 64 or (k > 64 and k not in streamBits)} self.__addLumiToStreamBits(rbs, substreamBits) # Make the expression for not-lumi-exclusive and add it to the routing bits writer -- GitLab From ec185a2abed3e8243bf9a4782ab5fa4d0a4e9e53 Mon Sep 17 00:00:00 2001 From: Roel Aaij <raaij@nikhef.nl> Date: Mon, 25 Apr 2016 19:09:57 +0200 Subject: [PATCH 2/3] Move 'Hlt2' to line names in HltOutputConf.Hlt2LinesForDQ --- Hlt/HltConf/python/HltConf/HltOutput.py | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/Hlt/HltConf/python/HltConf/HltOutput.py b/Hlt/HltConf/python/HltConf/HltOutput.py index a6b66f59a..07806346f 100644 --- a/Hlt/HltConf/python/HltConf/HltOutput.py +++ b/Hlt/HltConf/python/HltConf/HltOutput.py @@ -83,10 +83,10 @@ class HltOutputConf(LHCbConfigurableUser): 'NanoBanks' : ['ODIN', 'HltLumiSummary', 'HltRoutingBits', 'DAQ'], 'LumiBankKillerAcceptFraction' : 0.9999, # fraction of lumi-only events where raw event is stripped down # (only matters if EnablelumiEventWriting = True) - 'Hlt2LinesForDQ' : ['PIDD02KPiTagTurboCalib', 'PIDLambda2PPiLLTurboCalib', 'PIDDetJPsiMuMuPosTaggedTurboCalib', - 'PIDDetJPsiMuMuNegTaggedTurboCalib', 'PIDLambda2PPiLLhighPTTurboCalib', 'PIDLambda2PPiLLveryhighPTTurboCalib', - 'DiMuonDetachedJPsi', 'PIDDs2PiPhiKKNegTaggedTurboCalib', 'PIDDs2PiPhiKKPosTaggedTurboCalib', - 'PIDDs2PiPhiKKUnbiasedTurboCalib'], + 'Hlt2LinesForDQ' : ['Hlt2PIDD02KPiTagTurboCalib', 'Hlt2PIDLambda2PPiLLTurboCalib', 'Hlt2PIDDetJPsiMuMuPosTaggedTurboCalib', + 'Hlt2PIDDetJPsiMuMuNegTaggedTurboCalib', 'Hlt2PIDLambda2PPiLLhighPTTurboCalib', 'Hlt2PIDLambda2PPiLLveryhighPTTurboCalib', + 'Hlt2DiMuonDetachedJPsi', 'Hlt2PIDDs2PiPhiKKNegTaggedTurboCalib', 'Hlt2PIDDs2PiPhiKKPosTaggedTurboCalib', + 'Hlt2PIDDs2PiPhiKKUnbiasedTurboCalib'], '_streams' : None # Cache property } @@ -339,7 +339,7 @@ class HltOutputConf(LHCbConfigurableUser): # RB 91 for the NOBIAS stream , 91 : "HLT_PASS('Hlt2MBNoBiasDecision')" # RB 92 for online DQ on HLT2 output - , 92 : "HLT_PASS_RE('Hlt2(%s)Decision')" % '|'.join(self.getProp("Hlt2LinesForDQ")) + , 92 : "HLT_PASS_RE('(%s)Decision')" % '|'.join(self.getProp("Hlt2LinesForDQ")) # RB 93 for SMOG physics; reserved # RB 94 LUMI stream , 94 : self.getProp('LumiPredicate') @@ -515,7 +515,7 @@ class HltOutputConf(LHCbConfigurableUser): # Always pass the HLT1 routing bits streamBits = set(self.knownStreams().values()) - rbs = {k : routingBits[k] for k in routingBits.iterkeys() if k < 64 or (k > 64 and k not in streamBits)} + rbs = {k : routingBits[k] for k in routingBits.iterkeys() if k < 64 or (k >= 64 and k not in streamBits)} self.__addLumiToStreamBits(rbs, substreamBits) # Make the expression for not-lumi-exclusive and add it to the routing bits writer -- GitLab From 14b2d9c71749db2c9b9417dd1b247f0c2224fbef Mon Sep 17 00:00:00 2001 From: Roel Aaij <raaij@nikhef.nl> Date: Mon, 25 Apr 2016 19:12:08 +0200 Subject: [PATCH 3/3] Improve comment. --- Hlt/HltConf/python/HltConf/HltOutput.py | 1 + 1 file changed, 1 insertion(+) diff --git a/Hlt/HltConf/python/HltConf/HltOutput.py b/Hlt/HltConf/python/HltConf/HltOutput.py index 07806346f..cf081ec42 100644 --- a/Hlt/HltConf/python/HltConf/HltOutput.py +++ b/Hlt/HltConf/python/HltConf/HltOutput.py @@ -514,6 +514,7 @@ class HltOutputConf(LHCbConfigurableUser): streamSequence.Members += [prepSequence] # Always pass the HLT1 routing bits + # and those HLT2 routing bits not corresponding to a logical stream streamBits = set(self.knownStreams().values()) rbs = {k : routingBits[k] for k in routingBits.iterkeys() if k < 64 or (k >= 64 and k not in streamBits)} self.__addLumiToStreamBits(rbs, substreamBits) -- GitLab