From 1d2634b97aa858fe0c27969a4e5051dcd335218c Mon Sep 17 00:00:00 2001
From: Rosen Matev <rosen.matev@cern.ch>
Date: Tue, 26 Apr 2016 11:03:35 +0200
Subject: [PATCH] Revert "Merge branch 'raaij-FixBit92' into 'master'
"

This reverts merge request !32
---
 Hlt/HltConf/python/HltConf/HltOutput.py | 12 +++++-------
 1 file changed, 5 insertions(+), 7 deletions(-)

diff --git a/Hlt/HltConf/python/HltConf/HltOutput.py b/Hlt/HltConf/python/HltConf/HltOutput.py
index 64b5aa1cf..812b23f71 100644
--- a/Hlt/HltConf/python/HltConf/HltOutput.py
+++ b/Hlt/HltConf/python/HltConf/HltOutput.py
@@ -83,9 +83,9 @@ class HltOutputConf(LHCbConfigurableUser):
                  'NanoBanks'              : ['ODIN', 'HltLumiSummary', 'HltRoutingBits', 'DAQ'],
                  'LumiBankKillerAcceptFraction' : 0.9999, # fraction of lumi-only events where raw event is stripped down
                                                           # (only matters if EnablelumiEventWriting = True)
-                 'Hlt2LinesForDQ'         : ['Hlt2PIDD02KPiTagTurboCalib', 'Hlt2PIDLambda2PPiLLTurboCalib', 'Hlt2PIDDetJPsiMuMuPosTaggedTurboCalib',
-                                             'Hlt2PIDDetJPsiMuMuNegTaggedTurboCalib', 'Hlt2PIDLambda2PPiLLhighPTTurboCalib', 'Hlt2PIDLambda2PPiLLveryhighPTTurboCalib',
-                                             'Hlt2DiMuonDetachedJPsi', 'Hlt2PIDDs2PiPhiKKNegTaggedTurboCalib', 'Hlt2PIDDs2PiPhiKKPosTaggedTurboCalib',
+                 'Hlt2LinesForDQ'         : ['PIDD02KPiTagTurboCalib', 'PIDLambda2PPiLLTurboCalib', 'PIDDetJPsiMuMuPosTaggedTurboCalib',
+                                             'PIDDetJPsiMuMuNegTaggedTurboCalib', 'PIDLambda2PPiLLhighPTTurboCalib', 'PIDLambda2PPiLLveryhighPTTurboCalib',
+                                             'DiMuonDetachedJPsi', 'Hlt2PIDDs2PiPhiKKNegTaggedTurboCalib', 'Hlt2PIDDs2PiPhiKKPosTaggedTurboCalib',
                                              'Hlt2PIDDs2PiPhiKKUnbiasedTurboCalib'],
                  '_streams'               : None # Cache property
                  }
@@ -339,7 +339,7 @@ class HltOutputConf(LHCbConfigurableUser):
                       # RB 91 for the NOBIAS stream
                       , 91 : "HLT_PASS('Hlt2MBNoBiasDecision')"
                       # RB 92 for online DQ on HLT2 output
-                      , 92 : "HLT_PASS_RE('(%s)Decision')" % '|'.join(self.getProp("Hlt2LinesForDQ"))
+                      , 92 : "HLT_PASS('Hlt2(%s)Decision')" % '|'.join(self.getProp("Hlt2LinesForDQ"))
                       # RB 93 for SMOG physics; reserved
                       # RB 94 LUMI stream
                       , 94 : self.getProp('LumiPredicate')
@@ -514,9 +514,7 @@ class HltOutputConf(LHCbConfigurableUser):
                 streamSequence.Members += [prepSequence]
 
                 # Always pass the HLT1 routing bits
-                # and those HLT2 routing bits not corresponding to a logical stream
-                streamBits = set(self.knownStreams().values())
-                rbs = {k : routingBits[k] for k in routingBits.iterkeys() if k < 64 or (k >= 64 and k not in streamBits)}
+                rbs = {k : routingBits[k] for k in routingBits.iterkeys() if k < 64}
                 self.__addLumiToStreamBits(rbs, substreamBits)
 
                 # Make the expression for not-lumi-exclusive and add it to the routing bits writer
-- 
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