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LHCb
LHCb
Commits
9e067c22
Commit
9e067c22
authored
3 years ago
by
Christopher Rob Jones
Browse files
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Plain Diff
RichDecoder - Do not make bit->anode lookup failure a hard assert error
parent
34e7f0e6
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1 merge request
!3061
Update RICH decoding for realistic cable maps from the pit
Changes
1
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1 changed file
Rich/RichFutureDAQ/src/component/RichRawBankDecoder.cpp
+79
-54
79 additions, 54 deletions
Rich/RichFutureDAQ/src/component/RichRawBankDecoder.cpp
with
79 additions
and
54 deletions
Rich/RichFutureDAQ/src/component/RichRawBankDecoder.cpp
+
79
−
54
View file @
9e067c22
...
...
@@ -60,6 +60,14 @@
using
namespace
Rich
::
Future
::
DAQ
;
using
namespace
Rich
::
DAQ
;
#ifndef NDEBUG
# define daq_debug( X ) _ri_debug << X;
# define daq_verbo( X ) _ri_verbo << X;
#else
# define daq_debug( X ) _ri_debug << X;
# define daq_verbo( X ) ;
#endif
namespace
Rich
::
Future
{
namespace
{
...
...
@@ -199,6 +207,12 @@ namespace Rich::Future {
/// PMT small/large flag mis-match
mutable
ErrorCounter
m_pmtSLFlagMismatch
{
this
,
"Small/Large PD flag mis-match"
};
/// Invalid zero suppressed bit to anode mapping
// mutable WarningCounter m_zsBitToAnodeInvalid{this, "Invalid ZS bit->anode mapping"};
/// Invalid none zero suppressed bit to anode mapping
// mutable WarningCounter m_nzsBitToAnodeInvalid{this, "Invalid NZS bit->anode mapping"};
};
}
// namespace Rich::Future
...
...
@@ -214,7 +228,7 @@ StatusCode RawBankDecoder::initialize() {
if
(
!
sc
)
return
sc
;
// force debug messages
//
sc = setProperty( "OutputLevel", MSG::VERBOSE );
sc
=
setProperty
(
"OutputLevel"
,
MSG
::
VERBOSE
);
// derived conditions
Tel40CableMapping
::
addConditionDerivation
(
this
);
...
...
@@ -245,7 +259,7 @@ OutData RawBankDecoder::operator()( const LHCb::RawEvent& rawEvent, //
OutData
decodedData
;
// Loop over data banks
for
(
const
auto
*
bank
:
richBanks
)
{
for
(
const
auto
*
const
bank
:
richBanks
)
{
// test bank is OK
if
(
UNLIKELY
(
!
bank
)
)
{
...
...
@@ -300,7 +314,7 @@ OutData RawBankDecoder::operator()( const LHCb::RawEvent& rawEvent, //
catch
(
const
GaudiException
&
expt
)
{
// count errors
++
m_rawReadErr
;
_ri
_verbo
<<
expt
.
message
()
<<
endmsg
;
daq
_verbo
(
expt
.
message
()
<<
endmsg
)
;
// dump the full bank
if
(
m_verboseErrors
)
{
dumpRawBank
(
*
bank
,
error
()
);
}
}
...
...
@@ -310,7 +324,7 @@ OutData RawBankDecoder::operator()( const LHCb::RawEvent& rawEvent, //
}
// bank loop
_ri
_debug
<<
"Decoded in total "
<<
richBanks
.
size
()
<<
" RICH Tel40 bank(s)"
<<
endmsg
;
daq
_debug
(
"Decoded in total "
<<
richBanks
.
size
()
<<
" RICH Tel40 bank(s)"
<<
endmsg
)
;
// return the fill map
return
decodedData
;
...
...
@@ -330,7 +344,7 @@ void RawBankDecoder::decodeToSmartIDs_MaPMT1( const LHCb::RawBank& bank,
// Get Tel40 Source ID
const
Rich
::
DAQ
::
SourceID
tel40ID
(
bank
.
sourceID
()
);
_ri
_debug
<<
"MaPMT1 Decoding Tel40 bank "
<<
tel40ID
<<
endmsg
;
daq
_debug
(
"MaPMT1 Decoding Tel40 bank "
<<
tel40ID
<<
endmsg
)
;
// Data bank size in 8 bit words
const
std
::
size_t
bankSize
=
bank
.
size
();
...
...
@@ -343,8 +357,7 @@ void RawBankDecoder::decodeToSmartIDs_MaPMT1( const LHCb::RawBank& bank,
// ... number of packed words
const
auto
nPackedSizeW
=
(
nTel40Links
/
2
)
+
(
nTel40Links
%
2
);
assert
(
bankSize
>=
(
std
::
size_t
)
nPackedSizeW
);
_ri_debug
<<
" -> Expecting "
<<
nTel40Links
<<
" Tel40 Links, "
//
<<
nPackedSizeW
<<
" packed header words"
<<
endmsg
;
daq_debug
(
" -> Expecting "
<<
nTel40Links
<<
" Tel40 Links, "
<<
nPackedSizeW
<<
" packed header words"
<<
endmsg
);
// Array to save sizes for each frame
std
::
array
<
PackedFrameSizes
::
IntType
,
Tel40CableMapping
::
MaxConnectionsPerTel40
>
connSizes
{};
...
...
@@ -354,9 +367,10 @@ void RawBankDecoder::decodeToSmartIDs_MaPMT1( const LHCb::RawBank& bank,
const
auto
NDataBits
=
std
::
numeric_limits
<
DT
>::
digits
;
// Loop over the first header words to extract the sizes in bytes
std
::
size_t
iWord
{
0
},
nPayloadWords
{
0
},
iPayloadWord
{
0
};
const
DT
*
dataW
=
bank
.
begin
<
DT
>
();
// outside for loop as reused below to decode payload
const
DT
*
bankEnd
=
bank
.
end
<
DT
>
();
// cache locally
std
::
size_t
iWord
{
0
},
nPayloadWords
{
0
},
iPayloadWord
{
0
};
const
DT
*
const
bankStart
=
bank
.
begin
<
DT
>
();
const
DT
*
dataW
=
bankStart
;
// outside for loop as reused below to decode payload
const
DT
*
const
bankEnd
=
bank
.
end
<
DT
>
();
// cache locally
for
(
;
iWord
<
nPackedSizeW
&&
dataW
!=
bankEnd
;
++
dataW
,
++
iWord
,
iPayloadWord
+=
2
)
{
// Extract the sizes from the packed word
const
PackedFrameSizes
sizes
(
*
dataW
);
...
...
@@ -367,14 +381,14 @@ void RawBankDecoder::decodeToSmartIDs_MaPMT1( const LHCb::RawBank& bank,
assert
(
(
std
::
size_t
)(
iWord
+
1
)
<
connSizes
.
size
()
);
connSizes
[
iPayloadWord
]
=
s1
;
connSizes
[
iPayloadWord
+
1
]
=
s0
;
//_ri
_verbo
<< "
Word " << iWord << " PackedSizeHeader " << sizes << endmsg;
daq
_verbo
(
" ->
Word "
<<
boost
::
format
(
"%02i"
)
%
iWord
<<
" PackedSizeHeader "
<<
sizes
<<
endmsg
)
;
}
// Validate the data sizes for each tel40 link extracted from the data
// is in agreement with the overall bank size
if
(
UNLIKELY
(
(
nPackedSizeW
+
nPayloadWords
)
!=
bankSize
)
)
{
++
m_bankSizeMisMatchErr
;
throw
Rich
::
Exception
(
"BankSize:"
+
std
::
to_string
(
bankSize
)
+
throw
Rich
::
Exception
(
"
Tel40:"
+
std
::
to_string
(
tel40ID
.
data
()
)
+
"
BankSize:"
+
std
::
to_string
(
bankSize
)
+
" != DecodedSize:"
+
std
::
to_string
(
nPackedSizeW
+
nPayloadWords
)
);
}
...
...
@@ -383,14 +397,14 @@ void RawBankDecoder::decodeToSmartIDs_MaPMT1( const LHCb::RawBank& bank,
std
::
size_t
iLink
{
0
};
while
(
dataW
!=
bankEnd
&&
iLink
<
connSizes
.
size
()
)
{
//_ri
_verbo
<<
"Link " << iLink << " Size " << (int)connSizes[iLink] << endmsg;
daq
_verbo
(
"Link "
<<
iLink
<<
" Size "
<<
(
int
)
connSizes
[
iLink
]
<<
endmsg
)
;
// Do we have any words to decode for this link
if
(
connSizes
[
iLink
]
>
0
)
{
// Get the Tel40 Data for this connection
const
auto
&
cData
=
connData
[
iLink
];
//_ri
_verbo
<<
" -> " << cData << endmsg;
daq
_verbo
(
" -> "
<<
cData
<<
endmsg
)
;
assert
(
cData
.
isValid
()
);
// get the PDMDB data
...
...
@@ -402,28 +416,34 @@ void RawBankDecoder::decodeToSmartIDs_MaPMT1( const LHCb::RawBank& bank,
// check MSB for this word
const
auto
isNZS
=
isBitOn
<
NDataBits
-
1
>
(
*
dataW
);
//_ri_verbo << " -> NZS=" << isNZS << " iW=" << iW << " " //
// << boost::format( "%02X" ) % (int)( *dataW ) //
// << "(" << std::bitset<NDataBits>( *dataW ) << ")" << endmsg;
daq_verbo
(
" -> NZS="
<<
isNZS
<<
" iW="
<<
iW
//
<<
" gW="
<<
iW
+
(
dataW
-
bankStart
)
<<
" "
//
<<
boost
::
format
(
"%02X"
)
%
(
int
)(
*
dataW
)
//
<<
"("
<<
std
::
bitset
<
NDataBits
>
(
*
dataW
)
<<
")"
<<
endmsg
);
if
(
LIKELY
(
!
isNZS
)
)
{
// ZS decoding... word is bit index
//_ri
_verbo
<<
" -> Bit Index " << (int)*dataW << endmsg;
daq
_verbo
(
" -> Bit Index "
<<
(
int
)
*
dataW
<<
endmsg
)
;
// load the anode data for this bit
assert
(
(
std
::
size_t
)(
*
dataW
)
<
frameData
.
size
()
);
const
auto
&
aData
=
frameData
[
*
dataW
];
//_ri_verbo << " -> " << aData << endmsg;
assert
(
aData
.
isValid
()
);
// make a smart ID
auto
hitID
=
cData
.
smartID
;
// sets RICH, side, module and PMT type
// Add the PMT and pixel info
hitID
.
setPD_EC_PMT
(
cData
.
moduleNum
.
data
(),
aData
.
ec
.
data
(),
aData
.
pmtInEC
.
data
()
);
hitID
.
setAnode_PMT
(
aData
.
anode
.
data
()
);
//_ri_verbo << " -> " << hitID << endmsg;
decodedIDs
.
emplace_back
(
hitID
);
daq_verbo
(
" -> "
<<
aData
<<
endmsg
);
// Data 'could' be invalid, e.g. radiation-induced-upsets
// so cannot make this a hard error
if
(
LIKELY
(
aData
.
isValid
()
)
)
{
// make a smart ID
auto
hitID
=
cData
.
smartID
;
// sets RICH, side, module and PMT type
// Add the PMT and pixel info
hitID
.
setPD_EC_PMT
(
cData
.
moduleNum
.
data
(),
aData
.
ec
.
data
(),
aData
.
pmtInEC
.
data
()
);
hitID
.
setAnode_PMT
(
aData
.
anode
.
data
()
);
daq_verbo
(
" -> "
<<
hitID
<<
endmsg
);
decodedIDs
.
emplace_back
(
hitID
);
}
else
{
//++m_zsBitToAnodeInvalid;
}
// move to next word
++
iW
;
...
...
@@ -447,16 +467,17 @@ void RawBankDecoder::decodeToSmartIDs_MaPMT1( const LHCb::RawBank& bank,
// if word zero clear MSB as this is the NZS flag
if
(
UNLIKELY
(
0
==
iNZS
)
)
{
setBitOff
<
NDataBits
-
1
>
(
nzsW
);
}
//_ri_verbo << " -> iNZS=" << iNZS << " " //
// << boost::format( "%02X" ) % (int)( nzsW ) //
// << "(" << std::bitset<NDataBits>( nzsW ) << ")" << endmsg;
daq_verbo
(
" -> iNZS="
<<
iNZS
//
<<
" gW="
<<
iNZS
+
(
dataW
-
bankStart
)
<<
" "
//
<<
boost
::
format
(
"%02X"
)
%
(
int
)(
nzsW
)
//
<<
"("
<<
std
::
bitset
<
NDataBits
>
(
nzsW
)
<<
")"
<<
endmsg
);
// does this word hold any active bits ?
if
(
nzsW
>
0
)
{
// Bit offset for this word
const
auto
bitOffset
=
halfBitOffset
+
(
NDataBits
*
(
nNZSwords
-
1
-
iNZS
)
);
//_ri
_verbo
<<
" -> Bit Offset " << (int)bitOffset << endmsg;
daq
_verbo
(
" -> Bit Offset "
<<
(
int
)
bitOffset
<<
endmsg
)
;
// word has data so loop over bits to extract
for
(
auto
iLB
=
0
;
iLB
<
NDataBits
;
++
iLB
)
{
...
...
@@ -465,21 +486,25 @@ void RawBankDecoder::decodeToSmartIDs_MaPMT1( const LHCb::RawBank& bank,
// form frame bit value
const
auto
bit
=
iLB
+
bitOffset
;
//_ri
_verbo
<<
" -> Bit Index " << (int)bit << endmsg;
daq
_verbo
(
" -> Bit Index "
<<
(
int
)
bit
<<
endmsg
)
;
// load the anode data for this bit
assert
(
(
std
::
size_t
)(
bit
)
<
frameData
.
size
()
);
const
auto
&
aData
=
frameData
[
bit
];
//_ri_verbo << " -> " << aData << endmsg;
assert
(
aData
.
isValid
()
);
// make a smart ID
auto
hitID
=
cData
.
smartID
;
// sets RICH, side, module and PMT type
// Add the PMT and pixel info
hitID
.
setPD_EC_PMT
(
cData
.
moduleNum
.
data
(),
aData
.
ec
.
data
(),
aData
.
pmtInEC
.
data
()
);
hitID
.
setAnode_PMT
(
aData
.
anode
.
data
()
);
//_ri_verbo << " -> " << hitID << endmsg;
decodedIDs
.
emplace_back
(
hitID
);
daq_verbo
(
" -> "
<<
aData
<<
endmsg
);
// Data 'could' be invalid, e.g. radiation-induced-upsets
// so cannot make this a hard error
if
(
LIKELY
(
aData
.
isValid
()
)
)
{
// make a smart ID
auto
hitID
=
cData
.
smartID
;
// sets RICH, side, module and PMT type
// Add the PMT and pixel info
hitID
.
setPD_EC_PMT
(
cData
.
moduleNum
.
data
(),
aData
.
ec
.
data
(),
aData
.
pmtInEC
.
data
()
);
hitID
.
setAnode_PMT
(
aData
.
anode
.
data
()
);
daq_verbo
(
" -> "
<<
hitID
<<
endmsg
);
decodedIDs
.
emplace_back
(
hitID
);
}
else
{
//++m_nzsBitToAnodeInvalid;
}
}
// bit is on
}
// loop over word bits
...
...
@@ -511,7 +536,7 @@ void RawBankDecoder::decodeToSmartIDs_StreamIDs( const LHCb::RawBank& bank,
// Get Tel40 Source ID
const
auto
Tel40ID
(
bank
.
sourceID
()
);
_ri
_debug
<<
"FlatList Decoding Tel40 bank "
<<
Tel40ID
<<
endmsg
;
daq
_debug
(
"FlatList Decoding Tel40 bank "
<<
Tel40ID
<<
endmsg
)
;
// Data bank size in 32 bit words
const
auto
bankSize
=
bank
.
size
()
/
4
;
...
...
@@ -565,7 +590,7 @@ void RawBankDecoder::fillDecodedData( const DecodedIDs& decodedIDs, //
// loop over the IDs to save
for
(
const
auto
id
:
decodedIDs
)
{
//_ri
_verbo
<<
" -> " << id << endmsg;
daq
_verbo
(
" -> "
<<
id
<<
endmsg
)
;
// The module number
const
Rich
::
DAQ
::
PDModuleNumber
mID
(
id
.
pdCol
()
);
...
...
@@ -596,11 +621,11 @@ void RawBankDecoder::fillDecodedData( const DecodedIDs& decodedIDs, //
if
(
LIKELY
(
mIt
==
mDataV
.
end
()
)
)
{
// make a new entry
mInfo
=
&
mDataV
.
emplace_back
(
mID
);
//_ri
_verbo
<<
" -> New Module " << mID << endmsg;
daq
_verbo
(
" -> New Module "
<<
mID
<<
endmsg
)
;
}
else
{
// use found entry
mInfo
=
&
(
*
mIt
);
//_ri
_verbo
<<
" -> Found Module " << mID << endmsg;
daq
_verbo
(
" -> Found Module "
<<
mID
<<
endmsg
)
;
}
// update cached info
last_mID
=
mID
;
...
...
@@ -608,7 +633,7 @@ void RawBankDecoder::fillDecodedData( const DecodedIDs& decodedIDs, //
}
else
{
// use cached info
mInfo
=
last_mInfo
;
//_ri
_verbo
<<
" -> Cached Module " << mID << endmsg;
daq
_verbo
(
" -> Cached Module "
<<
mID
<<
endmsg
)
;
}
// Find PD data object
...
...
@@ -620,11 +645,11 @@ void RawBankDecoder::fillDecodedData( const DecodedIDs& decodedIDs, //
pdInfo
=
&
mInfo
->
emplace_back
(
pdID
);
// Add to active PD count for current rich
decodedData
.
addToActivePDs
(
rich
);
//_ri
_verbo
<<
" -> New PD " << pdID << endmsg;
daq
_verbo
(
" -> New PD "
<<
pdID
<<
endmsg
)
;
}
else
{
// Use found entry
pdInfo
=
&
(
*
pdIt
);
//_ri
_verbo
<<
" -> Found PD " << pdID << endmsg;
daq
_verbo
(
" -> Found PD "
<<
pdID
<<
endmsg
)
;
}
// update the PD cache
last_pdID
=
pdID
;
...
...
@@ -632,7 +657,7 @@ void RawBankDecoder::fillDecodedData( const DecodedIDs& decodedIDs, //
}
else
{
// use last PD cache
pdInfo
=
last_pdInfo
;
//_ri
_verbo
<<
" -> Cached PD " << pdID << endmsg;
daq
_verbo
(
" -> Cached PD "
<<
pdID
<<
endmsg
)
;
}
// add the hit to the list
...
...
@@ -656,7 +681,7 @@ void RawBankDecoder::dumpRawBank( const LHCb::RawBank& bank, MsgStream& os ) con
const
auto
bankSize
=
bank
.
size
();
const
std
::
string
&
LINES
=
"-------------------------------------------------------------------"
"-----------------
--------------------------
"
;
"-----------------"
;
os
<<
LINES
<<
endmsg
;
os
<<
"RawBank version="
<<
version
<<
" SourceID="
<<
sID
.
data
()
<<
" datasize(bytes)="
//
<<
bankSize
<<
" magic="
<<
boost
::
format
(
"%04X"
)
%
bank
.
magic
()
<<
endmsg
;
...
...
@@ -665,13 +690,13 @@ void RawBankDecoder::dumpRawBank( const LHCb::RawBank& bank, MsgStream& os ) con
// Is this an empty bank ?
if
(
bankSize
>
0
)
{
using
Dtype
=
std
::
uint8_t
;
const
unsigned
int
cli_rowwidth
=
8
;
const
unsigned
int
cli_rowwidth
=
6
;
std
::
size_t
iWord
=
0
;
for
(
const
Dtype
*
dataW
=
bank
.
begin
<
Dtype
>
();
dataW
!=
bank
.
end
<
Dtype
>
();
++
dataW
)
{
// start new line
if
(
iWord
%
cli_rowwidth
==
0
)
{
if
(
0
!=
iWord
)
{
os
<<
endmsg
;
}
os
<<
boost
::
format
(
"%04
X
| "
)
%
iWord
;
os
<<
boost
::
format
(
"%04
i
| "
)
%
iWord
;
}
// print the byte
os
<<
boost
::
format
(
"%02X"
)
%
(
int
)(
*
dataW
);
...
...
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