This is an enhancement in the v302b data format. Any fully compliant
unpacker should only look for VFAT data when this bit is set. When this
bit is not set, the "VFAT block" must be skipped or interpreted
appropriately, if defined.

For each L1A, additional consecutive L1A are sent to the whole system,
leading to additional events. The additional L1A are flagged as such in
the event payload in order to help the unpacking software reconstruct
the precise event timing.

While effectively a multi-BX readout, this new mode is qualified of
"fake" since it is incompatible with any DAQLink output. Only the local
DAQ can be used. Additionally, no processing is implemented in firmware
and all decoding and reconstruction has to be done in software.

* Remove useless VFAT header checks

* Check for AMC-VFAT EC and BC mismatches

* Define the event size for the number of VFAT in the system

* Consider the VFAT packets with an out-of-range BC as invalid

* Only zero-suppress the valid VFAT blocks

* Suppress the invalid VFAT blocks following user's configuration

remove FIFOs for GBTX, they are not necessary because there's a DPRAM CDC in the gearbox when using RX_OPTIMIZATION = 0

This commit adds an option to select whether the sub lpGBT IC
communication RX should go through the sub lpGBT IC channel or the boss
lpGBT EC channel. The former option involves less the boss, but requires
(partial) blind configuration of the sub; the latter option involves
more the boss, but allows fully checked configuration of the sub.

Note how the boss lpGBT configuration requires an update. Indeed, the
ROM configuration sets the EPTXEcTriState bit in simplex mode (bit 1 of
EPTXEcChnCntr [0x0ac]). The usage of a tri-state driver requires to
enable the internal pull-up on the receiver side (EPRXECPullUpEnable
[bit 0] of EPRXEcChnCntr [0x0ec]).

Considering the first tests as well as the strict behavior of the online
software on error checking, the option is enabled by default. No change
in case of blind unchecked transactions is expected. The old behavior
can be restored by setting the BEFE.GEM.GEM_SYSTEM.CTRL.GBT_IC_RX_USE_EC
register to 0.

see: emu/0xbefe!119

because these feed into the sbit_delay block (which runs on the 40MHz clock), having the remapping
take place on the 160MHz clock will cause issues with alignment of sbits.. zero delay s-bits will be
coming in at different phase than non-zero-delay

The right solution may be to simply change the s-bit delay to operate on the 160MHz clock, and
make it so that the delay increments in 4*the set value

I should not have removed this, oops...

The Xilinx documentation of the XPM_FIFO_SYNC macro reads "A write
operation is performed when the FIFO is not full and wr_en is asserted
on each wr_clk cycle." This behaviour is true regardless of the rd_en
state.

In our specific case, that means that the cluster DAQ FIFO was
systematically overflowing when leaving the FILLING state/entering the
RUNNING state. Would the triggering cluster occur at the same clock
cycle, it would be lost.

Since we must avoid to completely fill the FIFO in the FILLING/RUNNING
states, one must start dropping words out of the FIFO one clock cycle
before the assertion of almost_full. Such a behavior can be implemented
with the help of the prog_full signal. Note the signal assertion
latency: the threshold must be set to SBIT_FIFO_DEPTH - 3 and not
SBIT_FIFO_DEPTH - 2.

With the fix implemented, the frozen clusters now systematically appear
where they should be in the cluster FIFO. More specifically, the readout
window works as follow:

* For a FIFO_TRIGGER_DELAY set to 0 BX, the triggering cluster always
  appears at BX 509.

* For a FIFO_TRIGGER_DELAY set to 509 BX, the triggering cluster always
  appears at BX 0.

* Values are always read in chronological order. Clusters before the
  triggering one are older; clusters after the triggering one are
  younger.

The behavior as well as the data integrity has been checked with an ILA.

Andrew Peck authored 2 years ago and Laurent Petre committed 2 years ago

this can be disabled through a programmable register