Switch off caching for RPC and TGC RDO To PRD decoding

Turning off the caching for the trigger RDO to PRD decoding of TGCs and RPCs. Due to the way the decoding is done, the caching was leading to some irreproducibilities depedning on the order in which RoIs were processed in cases where we had somewhat overlapping RoIs. Depending on the order in which RoIs were processed, we were sometimes picking up cached hits from outside of a given RoI. The full explanation of the problem is in ATR-27454 (also should fix ATR-26908 and ATR-27154).

MuonSpectrometer/MuonConfig/python/MuonRdoDecodeConfig.py

@@ -73,8 +73,8 @@ def RpcRDODecodeCfg(flags, name="RpcRdoToRpcPrepData", **kwargs):
     # Get the RDO -> PRD tool
     kwargs.setdefault("DecodingTool", CompFactory.Muon.RpcRdoToPrepDataToolMT(name="RpcPrepDataProviderTool",
                                                                               ReadKey="RpcCondDbData" if not flags.Common.isOnline else "",
-                                                                              RpcPrdContainerCacheKey=MuonPrdCacheNames.RpcCache if flags.Muon.MuonTrigger else "",
-                                                                              RpcCoinDataContainerCacheKey=MuonPrdCacheNames.RpcCoinCache if flags.Muon.MuonTrigger else "",
+                                                                              RpcPrdContainerCacheKey="",
+                                                                              RpcCoinDataContainerCacheKey="",
                                                                               **tool_kwargs))
 
     # add RegSelTool
@@ -102,8 +102,8 @@ def TgcRDODecodeCfg(flags, name="TgcRdoToTgcPrepData", **kwargs):
 
     # Get the RDO -> PRD tool
     kwargs.setdefault("DecodingTool", CompFactory.Muon.TgcRdoToPrepDataToolMT(name="TgcPrepDataProviderTool",
-                                                                              PrdCacheString = MuonPrdCacheNames.TgcCache if flags.Muon.MuonTrigger else "",
-                                                                              CoinCacheString = MuonPrdCacheNames.TgcCoinCache if flags.Muon.MuonTrigger else ""))
+                                                                              PrdCacheString = "",
+                                                                              CoinCacheString = ""))
 
     # add RegSelTool
     from RegionSelector.RegSelToolConfig import regSelTool_TGC_Cfg

Trigger/TrigValidation/TrigP1Test/share/ref_v1Dev_decodeBS_build.ref

@@ -7601,24 +7601,24 @@ HLT_mu4_L1MU3V:
   stepCounts:
     0: 10
     1: 8
-    2: 5
+    2: 4
     3: 4
   stepFeatures:
     0: 11
     1: 8
-    2: 5
+    2: 4
     3: 4
 HLT_mu4_bJpsimutrk_MuonTrkPEB_L1MU3V:
   eventCount: 0
   stepCounts:
     0: 10
     1: 5
-    2: 5
+    2: 4
     3: 4
   stepFeatures:
     0: 11
     1: 6
-    2: 5
+    2: 4
     3: 4
     4: 4
 HLT_mu4_bJpsimutrk_MuonTrkPEB_L1MU3VF:
@@ -7626,12 +7626,12 @@ HLT_mu4_bJpsimutrk_MuonTrkPEB_L1MU3VF:
   stepCounts:
     0: 8
     1: 4
-    2: 4
+    2: 3
     3: 3
   stepFeatures:
     0: 9
     1: 5
-    2: 4
+    2: 3
     3: 3
     4: 3
 HLT_mu4_ivarloose_2mu3noL1_L1BPH-7M14-0DR25-MU5VFMU3VF:
@@ -7717,14 +7717,14 @@ HLT_mu4_j20_0eta290_020jvt_boffperf_pf_ftf_dRAB03_L1MU3V_J15:
   stepCounts:
     0: 5
     1: 4
-    2: 3
+    2: 2
     3: 2
     4: 2
     5: 2
   stepFeatures:
     0: 5
     1: 4
-    2: 3
+    2: 2
     3: 2
     4: 2
     5: 8
@@ -7734,14 +7734,14 @@ HLT_mu4_j20_0eta290_020jvt_boffperf_pf_ftf_dRAB03_L1MU3V_jJ40:
   stepCounts:
     0: 6
     1: 5
-    2: 4
+    2: 3
     3: 3
     4: 3
     5: 3
   stepFeatures:
     0: 6
     1: 5
-    2: 4
+    2: 3
     3: 3
     4: 3
     5: 10
@@ -7751,7 +7751,7 @@ HLT_mu4_j20_0eta290_020jvt_boffperf_pf_ftf_dRAB04_L1MU3V:
   stepCounts:
     0: 10
     1: 8
-    2: 5
+    2: 4
     3: 4
     4: 4
     5: 4
@@ -7759,7 +7759,7 @@ HLT_mu4_j20_0eta290_020jvt_boffperf_pf_ftf_dRAB04_L1MU3V:
   stepFeatures:
     0: 11
     1: 8
-    2: 5
+    2: 4
     3: 4
     4: 4
     5: 12
@@ -7769,7 +7769,7 @@ HLT_mu4_j20_0eta290_boffperf_pf_ftf_dRAB03_L1MU3V:
   stepCounts:
     0: 10
     1: 8
-    2: 5
+    2: 4
     3: 4
     4: 4
     5: 4
@@ -7777,7 +7777,7 @@ HLT_mu4_j20_0eta290_boffperf_pf_ftf_dRAB03_L1MU3V:
   stepFeatures:
     0: 11
     1: 8
-    2: 5
+    2: 4
     3: 4
     4: 4
     5: 17
@@ -7787,7 +7787,7 @@ HLT_mu4_j20_0eta290_boffperf_pf_ftf_dRAB04_L1MU3V_J12:
   stepCounts:
     0: 6
     1: 5
-    2: 4
+    2: 3
     3: 3
     4: 3
     5: 3
@@ -7795,7 +7795,7 @@ HLT_mu4_j20_0eta290_boffperf_pf_ftf_dRAB04_L1MU3V_J12:
   stepFeatures:
     0: 6
     1: 5
-    2: 4
+    2: 3
     3: 3
     4: 3
     5: 15
@@ -7805,7 +7805,7 @@ HLT_mu4_j20_0eta290_boffperf_pf_ftf_dRAB04_L1MU3V_jJ30:
   stepCounts:
     0: 6
     1: 5
-    2: 4
+    2: 3
     3: 3
     4: 3
     5: 3
@@ -7813,7 +7813,7 @@ HLT_mu4_j20_0eta290_boffperf_pf_ftf_dRAB04_L1MU3V_jJ30:
   stepFeatures:
     0: 6
     1: 5
-    2: 4
+    2: 3
     3: 3
     4: 3
     5: 15
@@ -7823,7 +7823,7 @@ HLT_mu4_j35_0eta290_020jvt_boffperf_pf_ftf_dRAB04_L1MU3V_J15:
   stepCounts:
     0: 5
     1: 4
-    2: 3
+    2: 2
     3: 2
     4: 2
     5: 1
@@ -7831,7 +7831,7 @@ HLT_mu4_j35_0eta290_020jvt_boffperf_pf_ftf_dRAB04_L1MU3V_J15:
   stepFeatures:
     0: 5
     1: 4
-    2: 3
+    2: 2
     3: 2
     4: 2
     5: 3
@@ -7841,14 +7841,14 @@ HLT_mu4_j35_0eta290_boffperf_pf_ftf_dRAB03_L1BTAG-MU3VjJ40:
   stepCounts:
     0: 2
     1: 2
-    2: 2
+    2: 1
     3: 1
     4: 1
     5: 1
   stepFeatures:
     0: 2
     1: 2
-    2: 2
+    2: 1
     3: 1
     4: 1
     5: 3
@@ -7858,7 +7858,7 @@ HLT_mu4_j35_0eta290_boffperf_pf_ftf_dRAB04_L1BTAG-MU3VjJ40:
   stepCounts:
     0: 2
     1: 2
-    2: 2
+    2: 1
     3: 1
     4: 1
     5: 1
@@ -7866,7 +7866,7 @@ HLT_mu4_j35_0eta290_boffperf_pf_ftf_dRAB04_L1BTAG-MU3VjJ40:
   stepFeatures:
     0: 2
     1: 2
-    2: 2
+    2: 1
     3: 1
     4: 1
     5: 3
@@ -7876,7 +7876,7 @@ HLT_mu4_j35_0eta290_boffperf_pf_ftf_dRAB04_L1MU3V_jJ40:
   stepCounts:
     0: 6
     1: 5
-    2: 4
+    2: 3
     3: 3
     4: 3
     5: 1
@@ -7884,7 +7884,7 @@ HLT_mu4_j35_0eta290_boffperf_pf_ftf_dRAB04_L1MU3V_jJ40:
   stepFeatures:
     0: 6
     1: 5
-    2: 4
+    2: 3
     3: 3
     4: 3
     5: 3
@@ -7894,7 +7894,7 @@ HLT_mu4_j45_0eta290_020jvt_boffperf_pf_ftf_dRAB04_L1MU3V_J15:
   stepCounts:
     0: 5
     1: 4
-    2: 3
+    2: 2
     3: 2
     4: 2
     5: 1
@@ -7902,7 +7902,7 @@ HLT_mu4_j45_0eta290_020jvt_boffperf_pf_ftf_dRAB04_L1MU3V_J15:
   stepFeatures:
     0: 5
     1: 4
-    2: 3
+    2: 2
     3: 2
     4: 2
     5: 2
@@ -7912,7 +7912,7 @@ HLT_mu4_j45_0eta290_boffperf_pf_ftf_dRAB04_L1BTAG-MU3VjJ40:
   stepCounts:
     0: 2
     1: 2
-    2: 2
+    2: 1
     3: 1
     4: 1
     5: 1
@@ -7920,7 +7920,7 @@ HLT_mu4_j45_0eta290_boffperf_pf_ftf_dRAB04_L1BTAG-MU3VjJ40:
   stepFeatures:
     0: 2
     1: 2
-    2: 2
+    2: 1
     3: 1
     4: 1
     5: 2
@@ -7930,7 +7930,7 @@ HLT_mu4_j45_0eta290_boffperf_pf_ftf_dRAB04_L1MU3V_jJ40:
   stepCounts:
     0: 6
     1: 5
-    2: 4
+    2: 3
     3: 3
     4: 3
     5: 1
@@ -7938,7 +7938,7 @@ HLT_mu4_j45_0eta290_boffperf_pf_ftf_dRAB04_L1MU3V_jJ40:
   stepFeatures:
     0: 6
     1: 5
-    2: 4
+    2: 3
     3: 3
     4: 3
     5: 2
@@ -7952,12 +7952,12 @@ HLT_mu4_l2io_L1MU3V:
   stepCounts:
     0: 10
     1: 5
-    2: 5
+    2: 4
     3: 4
   stepFeatures:
     0: 11
     1: 6
-    2: 5
+    2: 4
     3: 4
 HLT_mu4_mu4_idperf_1invmAB5_L12MU3VF:
   eventCount: 0
@@ -8134,13 +8134,13 @@ HLT_mu6_j60_0eta290_020jvt_boffperf_pf_ftf_dRAB04_L1MU3V_J15:
   stepCounts:
     0: 5
     1: 3
-    2: 2
+    2: 1
     3: 1
     4: 1
   stepFeatures:
     0: 5
     1: 3
-    2: 2
+    2: 1
     3: 1
     4: 1
 HLT_mu6_j60_0eta290_boffperf_pf_ftf_dRAB04_L1BTAG-MU3VjJ40:
@@ -8148,23 +8148,21 @@ HLT_mu6_j60_0eta290_boffperf_pf_ftf_dRAB04_L1BTAG-MU3VjJ40:
   stepCounts:
     0: 2
     1: 1
-    2: 1
   stepFeatures:
     0: 2
     1: 1
-    2: 1
 HLT_mu6_j60_0eta290_boffperf_pf_ftf_dRAB04_L1MU3V_jJ40:
   eventCount: 0
   stepCounts:
     0: 6
     1: 4
-    2: 3
+    2: 2
     3: 2
     4: 2
   stepFeatures:
     0: 6
     1: 4
-    2: 3
+    2: 2
     3: 2
     4: 2
 HLT_mu6_l2io_mu4_l2io_invmDimu_L1BPH-2M9-0DR15-C-MU5VFMU3V: