Intellegent command buffer
We have been discussing this on and off, but i think it's time we reach a conclusion on this. To optimize scan times, it is desirable to have more detailed control over how the FPGA sends / repeats commands to the chip.
A quick-and-dirty workaround could be to just increase the available buffer size. Already a size of 10KB (instead of 4KB at the moment) could mage a large difference. This should be possible to be implemented without problems, right @matvogt ?
The nicer and more long-term solution however might be to add some more gradual control over which commands have to be sent once and which should be repeated.
Option 1: A buffer structure like PREFIX
REPETITION BLOCK
POSTFIX
is already a nice solution for many cases.
Option 2: Multiple (at least two, maybe more) equal buffers of same size, sent one after the other
- This could enable us to fill one buffer while another one is being sent / repeated
- Possibly the fastest end result?
@dphol, @hemperek, @ydieter, @matvogt what do you think is the best solution?
@matvogt how hard is it to implement the different options?