Tweaks and FAQ

FAQ

If you encounter problems running scans, make sure to check:

• Power (+cables): Good cables (at least 0.75 mm²), not (much) longer than necessary are highly recommended. It's a good idea to measure the supply voltage(s) on the single chip card to identify excessive voltage drop in the cables.

  In direct powering mode, try to increase VDDA and VDDD to 1.25 V instead of 1.2 V.

• Firmware has been flashed and is compatible with your BDAQ53 software version.

• The FPGA is responding: Connect the readout system to a dedicated Ethernet interface, configured with a static IP in the 192.168.10.x net, for example 192.168.10.1. Try to ping the readout system on its default address: ping 192.168.10.16.

• The CMD lines are not swapped (only applies to KC705 and USBPix3 setups with separate adapter cards or cables). If they are, you will most likely see an error message like ERROR Timeout while waiting for chip status.

• Debug LED configuration on BDAQ53, USBPix3 and KC705 boards:

  LED	Function	comments
  0	LOCKED	FPGA PLL (for state machine etc.) is locked
  1	AUR_PLL_LOCKED	The reference clock PLL (160 MHz for the Aurora RX) is locked
  2	AUR_RX_CHANNEL_UP	An Aurora data stream input has been detected
  3	AUR_RX_LANE_UP	The Aurora receiver has synchronized the the data stream. Blinking: Link is lost
  4	FIFO_FULL	RX buffer overflow
  5	TCP_TX_WR	Data is sent to the readout PC
  6	TCP_RX_WR	Data is received from the readout PC
  7	TCP_OPEN_ACK	An Ethernet connection to the readout PC has been established

  A stable link to the chip is indicated by LED2 and LED3.

• Resetting the Aurora receiver: For debugging purposes it can be useful to reset the Aurora receiver and let it re-establish the link to the chip. To do so, press the "USER" push button of the BDAQ53 or USBPix3 (MIO3/MMC3) base board or the "CENTER" button if you are using the KC705.

Tweaks

• To streamline unittest output, edit your cocotb makefile located in [cocotb]/makefiles/simulators/Makefile.[your simulator] and change | tee sim.log to > sim.log in line 140. This disables the console output from cocotb compilation.

Firmware synthesis in Windows

The installation process for Windows is very similar to Linux.

• You will need the latest Conda for Windows, git and Vivado (in this example, we assume you installed Vivado 2018.1 to the default directory).

• Then, browse to C:\Xilinx\Vivado\2018.1\. The standard procedure is to start this batch script, in order to set the needed environmental variables in Windows. However, if this doesn't work, it is necessary to set the paths manually .First, open the file .settings64-Vivado.bat. It should look like this:

  `@echo off REM ################################################################# REM # Copyright (c) 1986-2019 Xilinx, Inc. All rights reserved. # REM #################################################################

  SET PATH=C:\Xilinx\Vivado\2018.1\bin;C:\Xilinx\Vivado\2018.1\lib\win64.o;%PATH%SET XILINX_VIVADO=C:\Xilinx\Vivado \2018.1`

• Now, decompose the parts of the last line to:

  1. SET PATH=
     • (1.1) C:\Xilinx\Vivado\2018.1\bin
     • (1.2) C:\Xilinx\Vivado\2018.1\lib\win64.o
  2. SET XILINX_VIVADO=C:\Xilinx\Vivado \2018.1

• Open the Windows Start Search, type env, select Edit the system environment variables, click the Environment Variables... button.

• In the upper half of the window, select the variable Path and click Edit.... In the edit windows, add both paths (1.1 and 1.2) by selecting New and then pasting the paths one by one.

• In the lower half of the windows, select New..., (according to 2.) copy and paste the path SET XILINX_VIVADO in the field Variable name and the path itself C:\Xilinx\Vivado \2018.1 into Variable value.

• Exit with OK and check if the new entries are made.
• In order to run the synthesis, open the installed Anaconda Prompt, follow the download and installation instructions for basil and bdaq. Then start the synthesis according to the readme.