WRG does not define correctly the voter width
Summary
WRG (wrapper-generator) does not define the voter width correctly for some signals.
TMRG Version
Steps to reproduce
Port definition:
module mspu_sram_ctrl #(
...
// Logging interface:
output [ 15 : 0 ] log_single_err_cnt_o,
output [ 15 : 0 ] log_double_err_cnt_o,
...
The signal affected is coming directly from a sub-module:
mspu_logging mspu_logging (
...
.single_err_cnt_o (log_single_err_cnt_o),
.double_err_cnt_o (log_double_err_cnt_o),
Command run :
wrg rtl/mspu_sram_ctrl.sv > test
What is the current bug behavior?
// voter for log_double_err_cnt_o
wire [15 : 0] log_double_err_cnt_oA;
wire [15 : 0] log_double_err_cnt_oB;
wire [15 : 0] log_double_err_cnt_oC;
wire log_double_err_cnt_otmrErr;
mspu_sram_ctrlVoter #(.WIDTH( 16 * (<bound method Signal.type_size of <tmrg.verilog_elaborator.Signal object at 0x7f2cfa0d52e8>>) )) log_double_err_cnt_oVoter (
.inA(log_double_err_cnt_oA),
.inB(log_double_err_cnt_oB),
.inC(log_double_err_cnt_oC),
.out(log_double_err_cnt_o),
.tmrErr(log_double_err_cnt_otmrErr)
);
What is the expected correct behavior?
// voter for log_double_err_cnt_o
wire [15 : 0] log_double_err_cnt_oA;
wire [15 : 0] log_double_err_cnt_oB;
wire [15 : 0] log_double_err_cnt_oC;
wire log_double_err_cnt_otmrErr;
mspu_sram_ctrlVoter #(.WIDTH( 16 )) log_double_err_cnt_oVoter (
.inA(log_double_err_cnt_oA),
.inB(log_double_err_cnt_oB),
.inC(log_double_err_cnt_oC),
.out(log_double_err_cnt_o),
.tmrErr(log_double_err_cnt_otmrErr)
);
Relevant logs and/or screenshots
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Possible fixes
(If you can, link to the line of code that might be responsible for the problem)