enum in FSM state produces warnings when elaborating in xcelium
Summary
The output of tmrg is not simulator-friendly.
Describe your setup
mosaix_rtl at REPRODUCED_111
(see https://gitlab.cern.ch/mosaix/mosaix_rtl/-/merge_requests/321#note_7879629)
TMRG Version
tmrg at REPRODUCED_111
Steps to reproduce
module a();
typedef enum logic [1:0] {FsmIdle = 2'b00, FsmWait_Sample = 2'b01, FsmTrans = 2'b11} state_t;
state_t state;
state_t state_next;
state_t state_nextVoted = state_next;
endmodule
What is the current bug behavior?
Output is
// [...]
typedef enum logic [1:0] {FsmIdle = 2'b00, FsmWait_Sample = 2'b01, FsmTrans = 2'b11} state_t;
state_t stateA;
state_t stateB;
state_t stateC;
state_t state_nextA;
state_t state_nextB;
state_t state_nextC;
state_t state_nextVotedA;
state_t state_nextVotedB;
state_t state_nextVotedC;
// [...]
majorityVoter_mosaix #(.WIDTH(2)) state_nextVoterA (
.inA(state_nextA),
.inB(state_nextB),
.inC(state_nextC),
.out(state_nextVotedA),
.tmrErr(state_nextTmrErrorA)
);
// [...]
endmodule;
// /projects/TOWER65/devel65/V1.0Tests/workAreas/pevicent/MOSAIX/mosaix_rtl/tools/tmrg/tmrg/../common/voter.v
module majorityVoter_mosaix #(
parameter WIDTH = 1
)(
input wire [WIDTH-1:0] inA,
input wire [WIDTH-1:0] inB,
input wire [WIDTH-1:0] inC,
output wire [WIDTH-1:0] out,
output reg tmrErr
);
assign out = (inA&inB) | (inA&inC) | (inB&inC);
always @(inA or inB or inC) begin
if (inA!=inB || inA!=inC || inB!=inC)
tmrErr = 1;
else
tmrErr = 0;
end
endmodule
When elaborating I see the following error
.out(state_nextVotedA),
|
*E,ENUMERR [...] This assignment is a violation of SystemVerilog strong typing rules for enumeration datatypes.
What is the expected correct behavior?
No warning
Possible fixes
Edited by Pedro Vicente Leitao