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Unsupported assertions in code

Summary

tmrg does not support SVA in code

Describe your setup

fastrich toolkit/serialisers/rtl/serializer_ddr_mux_slave.sv

TMRG Version

REPRODUCED_111

Steps to reproduce

module test (input clk_i);
int idx;
logic input_sampled;
logic deserialized;
assert property (@(clk_i) (idx==0) & ~$isunknown($past(input_sampled, 5)) |-> (deserialized == $past(input_sampled, 5)));
endmodule

What is the current bug behavior?

$ tmrg test.sv 
[ERROR  ] Error in file 'test.sv' around line '5'.
[ERROR  ] 
[ERROR  ] assert property (@(clk_i) (idx==0) & ~$isunknown($past(input_sampled, 5)) |-> (deserialized == $past(input_sampled, 5)));
[ERROR  ] ^
[ERROR  ] Expected module, found 'assert'  (at char 77), (line:5, col:1)
[ERROR  ] Error during parsing

What is the expected correct behavior?

Assertion should pass to the output (triplicated if needed)

Possible fixes