tmrg removes delayed assignments

Summary

tmrg is removing important syntax

Describe your setup

fastrich

TMRG Version

REPRODUCED_136

Steps to reproduce

module test;
  logic a,b;
  assign #(1:2:3) a = b;
endmodule

What is the current bug behavior?

module testTMR;
logic aA;
logic aB;
logic aC;
logic bA;
logic bB;
logic bC;
assign aA = bA;
assign aB = bB;
assign aC = bC;
endmodule

What is the expected correct behavior?

module testTMR;
logic aA;
logic aB;
logic aC;
logic bA;
logic bB;
logic bC;
assign #(1:2:3) aA = bA;
assign #(1:2:3) aB = bB;
assign #(1:2:3) aC = bC;
endmodule

Possible fixes

(If you can, link to the line of code that might be responsible for the problem)