Bug in processing nested generate/if statements
Test case:
module test(
input resetb,
input clk40
);
genvar i;
generate
for (i=0; i<=8; i=i+1) begin : loop
if (i<=8) begin
ModuleBase Module_0
(
.clk40_fc(clk40)
);
end
if (i==8) begin
ModuleSpecial ModuleSpecial_0
(
.clk(clk40)
);
end
end
endgenerate
endmodule
Reported by @fdulucq.