Incorrect output when port names are similar
Test case:
module top (output E1A);
// tmrg default triplicate
mod d0 (.E1(E1A));
endmodule
module mod (output E1);
// tmrg default triplicate
endmodule
TMRG output:
module topTMR(
output E1AA,
output E1AB,
output E1AC
);
modTMR d0 (
.E1AA(E1AA), <<< expected: .E1A(E1AA)
.E1B(E1AB),
.E1C(E1AC)
);
endmodule
module modTMR(
output E1A,
output E1B,
output E1C
);
endmodule
Reported by Datao.