Add support for `always_comb`
Problem to solve
always_comb
construct is not supported as it is part of SystemVerilog standard.
The keyword should be supported as equivalent to always
in the case of combinatorial logic (arbitrary sensitivity list).
Target audience
Proposal
-
Add this module to the list of tests (failure expected) -
Modify the tool to add the support for this code snippet
What does success look like, and how can we measure that?
- Newly added test passes.
Edited by Matteo Lupi