Add support for enumerated types

Problem to solve

enum typedef construct is not supported as it is part of SystemVerilog standard. The implementation of this construct should be supported both on in the code (defining signals of a specific enum type) or in the module call list. The enum to be supported, can be limited to a definition which specifies the number of bits of the type. E.g.

  typedef enum    bit [1:0]   {
    GRAY2_ST0   =   2'b00,
    GRAY2_ST1   =   2'b01,
    GRAY2_ST2   =   2'b11,
    GRAY2_ST3   =   2'b10
  }   grayCode_2bit_t;

The width of the signals, e.g. for grayCode_2bit_t aenum, needed to instantiate the voters of the correct width, can be calculated with $clog2(aenum.num()), $bits(aenum), or $bits(grayCode_2bit_t). The first option returns the effective number of bits used, the second and third option return the number of bits the type is defined with.

E.g. for the example below the three options return the same value, i.e. 2.

  typedef enum    bit [1:0]   {
    GRAY2_ST0   =   2'b00,
    GRAY2_ST1   =   2'b01,
    GRAY2_ST2   =   2'b11,
    GRAY2_ST3   =   2'b10
  }   grayCode_2bit_t;

E.g. for the example below, the first option returns 1, whereas the two other option return 2.

  typedef enum    bit [1:0]   {
    GRAY2_ST0   =   2'b00,
    GRAY2_ST1   =   2'b01
  }   grayCode_2bit_t;

Target audience

@mlupi

Proposal

• Add this module to the list of tests (failure expected)
• Modify the tool to add the support for this code snippet

What does success look like, and how can we measure that?

• Newly added test passes.