TBG does not correctly recognises unpacked arrays as ports
Summary
TBG does not handle unpacked array correctly at the I/Os of the module
TMRG Version
Steps to reproduce
Run TBG on test.sv
module test
(input reg a [3],
output reg b [4]);
endmodule
What is the current bug behavior?
Output is
Click to expand
[mlupi@lxmicp013 seu]$ ../../utils/tmrg/bin/tbg test.sv
`timescale 1 ps / 1 ps
module majorityVoterTB #(
parameter WIDTH = 1
)(
input wire [WIDTH-1:0] inA,
input wire [WIDTH-1:0] inB,
input wire [WIDTH-1:0] inC,
output wire [WIDTH-1:0] out,
output reg tmrErr
);
assign out = (inA&inB) | (inA&inC) | (inB&inC);
always @(inA or inB or inC) begin
if (inA!=inB || inA!=inC || inB!=inC)
tmrErr = 1;
else
tmrErr = 0;
end
endmodule
module test_test;
// - - - - - - - - - - - - - - Parameters section - - - - - - - - - - - - - -
// - - - - - - - - - - - - - - Input/Output section - - - - - - - - - - - - -
reg a;
wire b;
// - - - - - - - - - - - - - Device Under Test section - - - - - - - - - - - -
`ifdef TMR
// fanout for a
wire aA=a;
wire aB=a;
wire aC=a;
// voter for b
wire bA;
wire bB;
wire bC;
wire btmrErr;
majorityVoterTB bVoter (
.inA(bA),
.inB(bB),
.inC(bC),
.out(b),
.tmrErr(btmrErr)
);
testTMR DUT (
.aA(aA),
.aB(aB),
.aC(aC),
.bA(bA),
.bB(bB),
.bC(bC)
);
`else
test DUT (
.a(a),
.b(b)
);
`endif
// - - - - - - - - - - - - Optional formal SEU injection section - - - - - - - - - - - - -
`ifdef TMR
`ifdef NETLIST
`ifdef FRMSVA
`include "seu_assert.sv"
`endif
`endif
`endif
// - - - - - - - - - - - - Timing annotation section - - - - - - - - - - - - -
`ifdef SDF
initial
$sdf_annotate("r2g.sdf", DUT, ,"sdf.log");
`endif
// - - - - - - - - - - - - Single Event Effect section - - - - - - - - - - - -
`ifdef SEE
reg SEEEnable=0; // enables SEE generator
reg SEEActive=0; // high during any SEE event
integer SEEnextTime=0; // time until the next SEE event
integer SEEduration=0; // duration of the next SEE event
integer SEEwireId=0; // wire to be affected by the next SEE event
integer SEEmaxWireId=0; // number of wires in the design which can be affected by SEE event
integer SEEmaxUpaseTime=1000; // 1 ns (change if you are using different timescale)
integer SEEDel=100_000; // 100 ns (change if you are using different timescale)
integer SEECounter=0; // number of simulated SEE events
`include "see.v"
// get number of wires which can be affected by see
initial
see_max_net (SEEmaxWireId);
always
begin
if (SEEEnable)
begin
// randomize time, duration, and wire of the next SEE
SEEnextTime = #(SEEDel/2) {$random} % SEEDel;
SEEduration = {$random} % (SEEmaxUpaseTime-1) + 1; // SEE time is from 1 - MAX_UPSET_TIME ns
SEEwireId = {$random} % SEEmaxWireId;
// wait for SEE
#(SEEnextTime);
// SEE happens here! Toggle the selected wire.
SEECounter=SEECounter+1;
SEEActive=1;
see_force_net(SEEwireId);
see_display_net(SEEwireId); // probably you want to comment this line ?
#(SEEduration);
see_release_net(SEEwireId);
SEEActive=0;
end
else
#10;
end
`endif
// - - - - - - - - - - - - - Actual testbench section - - - - - - - - - - - -
initial
begin
a=0;
`ifdef SEE
// enable SEE after 1ms
#1000_000 SEEEnable=1;
$display("Enabling SEE generation");
`endif
// finish simulation after 1ms
#1000_000 $finish;
end
endmodule
What is the expected correct behavior?
Unpacked arrays correctly recognised by TBG