Support left-hand side concatenation
Problem to solve
Support left-hand side concatenation.
Target audience
Further details
The following test-case is not supported.
module tmp(
input logic[3:0] in,
output logic[1:0] out0,
output logic[1:0] out1
);
//tmrg default triplicate
assign {out1, out0} = in;
endmodule
Proposal
Add support for the test case. This should be part of verilog (LRM to be checked).