return_value_function produces incorrect code
Summary
-
return_value_function.sv
testcase produces incorrect syntax - testcase is not triggered
TMRG Version
master
: fa519db1
Steps to reproduce
tmrg test/asicworld/systemverilog/return_value_function.sv
What is the current bug behavior?
- loop variable declaration changes name
- missing semicolon in return statement
module return_value_functionTMR;
initial
begin
$display("Value returned from function = %g", printI());
#1 $finish;
end
function int printI;
begin
for(int iA = 0; i<10; i++) << DECLARATION OF LOOP VARIABLE
begin
if (i>=5)
begin
return I << MISSING SEMICOLON
end
$display("Current value of i = %g", i);
end
end
endfunction
endmodule
What is the expected correct behavior?
module return_value_functionTMR;
initial
begin
$display("Value returned from function = %g", printI());
#1 $finish;
end
function int printI;
begin
for(int i = 0; i<10; i++)
begin
if (i>=5)
begin
return I;
end
$display("Current value of i = %g", i);
end
end
endfunction
endmodule
Relevant logs and/or screenshots
(Paste any relevant logs - please use code blocks (```) to format console output, logs, and code as it's very hard to read otherwise.)
Possible fixes
- missing return statement:
verilog_formatter.py:602
- add semicolon - declaration: ?