Indexes and hierarchical signals in the `generate` statement are improperly handled.

Summary

Indexes and hierarchical signals in the generate statement are improperly handled.

TMRG Version

af848b87

Steps to reproduce

module generate07 #(
    parameter N  = 4
) (
    input clk,
    input data_i,
    output data_o
);
  // tmrg default triplicate
  // tmrg do_not_triplicate j N
  genvar j;
  generate
    for (j = 0; j < N; j = j + 1) begin : gen_comb_stage
      wire comb_in;
      wire comb_out;

      if (j == 0) begin
          assign comb_in = data_i;
      end else  begin
          assign comb_in = gen_comb_stage[j-1].comb_out;
      end

      if (i == N-1) begin 
        assign data_o = comb_out;
      end

    end
  endgenerate
endmodule

What is the current bug behavior?

module generate07TMR #(
    parameter N = 4
)(
  input clkA,
  input clkB,
  input clkC,
  input data_iA,
  input data_iB,
  input data_iC,
  output data_oA,
  output data_oB,
  output data_oC
);
genvar j;

generate
  for(j = 0;j<N;j = j + 1)
    begin : gen_comb_stage 
      wire comb_inA;
      wire comb_inB;
      wire comb_inC;
      wire comb_outA;
      wire comb_outB;
      wire comb_outC;
      if (j==0)        begin 
          assign comb_inA = data_iA;
          assign comb_inB = data_iB;
          assign comb_inC = data_iC;
        end
      else        begin 
          assign comb_inA = gen_comb_stage[j-1].comb_out;  // BUG / UNSUPPORTED SYNTAX
          assign comb_inB = gen_comb_stage[j-1].comb_out;  // BUG / UNSUPPORTED SYNTAX
          assign comb_inC = gen_comb_stage[j-1].comb_out;  // BUG / UNSUPPORTED SYNTAX
        end
      if (i==N-1)        begin 
          assign data_oA = comb_outA;
          assign data_oB = comb_outB;
          assign data_oC = comb_outC;
        end
    end

endgenerate
endmodule

What is the expected correct behavior?

module generate07TMR #(
    parameter N = 4
)(
  input clkA,
  input clkB,
  input clkC,
  input data_iA,
  input data_iB,
  input data_iC,
  output data_oA,
  output data_oB,
  output data_oC
);
genvar j;

generate
  for(j = 0;j<N;j = j + 1)
    begin : gen_comb_stage 
      wire comb_inA;
      wire comb_inB;
      wire comb_inC;
      wire comb_outA;
      wire comb_outB;
      wire comb_outC;
      if (j==0)        begin 
          assign comb_inA = data_iA;
          assign comb_inB = data_iB;
          assign comb_inC = data_iC;
        end
      else        begin 
          assign comb_inA = gen_comb_stage[j-1].comb_outA;  // EXPECTED
          assign comb_inB = gen_comb_stage[j-1].comb_outB;  // EXPECTED
          assign comb_inC = gen_comb_stage[j-1].comb_outC;  // EXPECTED
        end
      if (i==N-1)        begin 
          assign data_oA = comb_outA;
          assign data_oB = comb_outB;
          assign data_oC = comb_outC;
        end
    end

endgenerate
endmodule

Target audience

@apaterno