diff --git a/test/test_tmrg.py b/test/test_tmrg.py
index 7ec8d2240de158128e2bc1c5cd7184ba43625523..7ff38f9e033014c9f482efa8b9d67f1510263320 100644
--- a/test/test_tmrg.py
+++ b/test/test_tmrg.py
@@ -197,7 +197,7 @@ class TestTmrgOnSingleSystemVerilogFile():
             "systemverilog/always_comb_04.sv",
             "systemverilog/package_import.sv",
             "systemverilog/always_comb_import.sv",
-            #"systemverilog/always_comb_import_unused_function.sv",
+            "systemverilog/always_comb_import_unused_function.sv",
             "systemverilog/always_comb_importstar.sv",
             "systemverilog/always_latch_01.sv",
             "systemverilog/always_latch_02.sv",