From e124a2cc9f497027f3d3b7ab0e1088e9c2f007ce Mon Sep 17 00:00:00 2001 From: Matteo Lupi <matteo.lupi@cern.ch> Date: Fri, 4 Feb 2022 11:46:54 +0100 Subject: [PATCH 1/2] ML added testcase --- test/systemverilog/forloop_generate03.sv | 51 ++++++++++++++++++++++++ test/test_tmrg.py | 1 + 2 files changed, 52 insertions(+) create mode 100644 test/systemverilog/forloop_generate03.sv diff --git a/test/systemverilog/forloop_generate03.sv b/test/systemverilog/forloop_generate03.sv new file mode 100644 index 00000000..8278628e --- /dev/null +++ b/test/systemverilog/forloop_generate03.sv @@ -0,0 +1,51 @@ +module ecc_reg + #(parameter NUM_REG_BITS = 8, + parameter NUM_SYNDROME_BITS = 5 + )( + input Clk, + input reset_b, + input [NUM_REG_BITS-1:0] w_din, + input w_en, + output logic [NUM_REG_BITS-1:0] reg_dout, + output logic single_bit_err, + output logic double_bit_err, + output logic parity_bit_err + ); +endmodule + + +module test + (input logic clk, + input logic reset_b); + + logic [9:0] a; + logic b [10]; + + always_comb + for (int i=0; i<10; i++) + b[i] = a[i]; + + logic [99:0] rw_ecc_w_en; + logic [7:0] rw_ecc_w_din [100]; + logic [7:0] rw_ecc_reg_dout [100]; + logic [99:0] rw_ecc_single_bit_err; + logic [99:0] rw_ecc_double_bit_err; + logic [99:0] rw_ecc_parity_bit_err; + + generate + for (genvar i=0; i<100; i++) begin + ecc_reg # (.NUM_REG_BITS (8), + .NUM_SYNDROME_BITS (5) + ) ecc_reg_u ( + .Clk (clk), + .reset_b (reset_b), + .w_din (rw_ecc_w_din [i]), + .w_en (rw_ecc_w_en [i]), + .reg_dout (rw_ecc_reg_dout [i]), + .single_bit_err (rw_ecc_single_bit_err [i]), + .double_bit_err (rw_ecc_double_bit_err [i]), + .parity_bit_err (rw_ecc_parity_bit_err [i]) + ); + end + endgenerate +endmodule diff --git a/test/test_tmrg.py b/test/test_tmrg.py index 50dabb1c..189f15a3 100644 --- a/test/test_tmrg.py +++ b/test/test_tmrg.py @@ -209,6 +209,7 @@ class TestTmrgOnSingleSystemVerilogFile(): "systemverilog/assignment_operators.sv", "systemverilog/forloop_generate01.sv", "systemverilog/forloop_generate02.sv", + "systemverilog/forloop_generate03.sv", "systemverilog/rhs_assign.sv", "systemverilog/forinalways.sv", "systemverilog/forinalwaysff.sv", -- GitLab From f967b040021e9c0a2492d49bfc5b0fd847c692ab Mon Sep 17 00:00:00 2001 From: Matteo Lupi <matteo.lupi@cern.ch> Date: Fri, 4 Feb 2022 12:15:54 +0100 Subject: [PATCH 2/2] ML added testcase --- test/systemverilog/forloop_generate04.sv | 43 ++++++++++++++++++++++++ test/test_tmrg.py | 1 + 2 files changed, 44 insertions(+) create mode 100644 test/systemverilog/forloop_generate04.sv diff --git a/test/systemverilog/forloop_generate04.sv b/test/systemverilog/forloop_generate04.sv new file mode 100644 index 00000000..bcd6c9f6 --- /dev/null +++ b/test/systemverilog/forloop_generate04.sv @@ -0,0 +1,43 @@ +module ecc_reg + #(parameter NUM_REG_BITS = 8, + parameter NUM_SYNDROME_BITS = 5 + )( + input Clk, + input reset_b, + input [NUM_REG_BITS-1:0] w_din, + input w_en, + output logic [NUM_REG_BITS-1:0] reg_dout, + output logic single_bit_err, + output logic double_bit_err, + output logic parity_bit_err + ); +endmodule + + +module test + (input logic clk, + input logic reset_b); + + logic [99:0] rw_ecc_w_en; + logic [7:0] rw_ecc_w_din [100]; + logic [7:0] rw_ecc_reg_dout [100]; + logic [99:0] rw_ecc_single_bit_err; + logic [99:0] rw_ecc_double_bit_err; + logic [99:0] rw_ecc_parity_bit_err; + + generate + for (genvar i=0; i<100; i++) + ecc_reg # (.NUM_REG_BITS (8), + .NUM_SYNDROME_BITS (5) + ) ecc_reg_u ( + .Clk (clk), + .reset_b (reset_b), + .w_din (rw_ecc_w_din [i]), + .w_en (rw_ecc_w_en [i]), + .reg_dout (rw_ecc_reg_dout [i]), + .single_bit_err (rw_ecc_single_bit_err [i]), + .double_bit_err (rw_ecc_double_bit_err [i]), + .parity_bit_err (rw_ecc_parity_bit_err [i]) + ); + endgenerate +endmodule diff --git a/test/test_tmrg.py b/test/test_tmrg.py index 189f15a3..c703f3fa 100644 --- a/test/test_tmrg.py +++ b/test/test_tmrg.py @@ -210,6 +210,7 @@ class TestTmrgOnSingleSystemVerilogFile(): "systemverilog/forloop_generate01.sv", "systemverilog/forloop_generate02.sv", "systemverilog/forloop_generate03.sv", + "systemverilog/forloop_generate04.sv", "systemverilog/rhs_assign.sv", "systemverilog/forinalways.sv", "systemverilog/forinalwaysff.sv", -- GitLab