Fix signed literal

The correct format of number literals in verilog is: ’value for example 2'sb11 is a signed binary number, at the moment it doesn't support signed notation. https://web.engr.oregonstate.edu/~traylor/ece474/beamer_lectures/verilog_number_literals.pdf

Hopefully, the fix passes regressions, I didnt know how to start them, CI will take care of it. I added a test signed_literal.v, but maybe I need to declare it somewhere else also, or give an expected output?