diff --git a/test/systemverilog/function_automatic1.sv b/test/systemverilog/function_automatic1.sv
new file mode 100644
index 0000000000000000000000000000000000000000..3b59f4b3e195a5a7b7c04b284e86b50314b93fc5
--- /dev/null
+++ b/test/systemverilog/function_automatic1.sv
@@ -0,0 +1,5 @@
+module test;
+  function automatic logic mux (logic a, logic b);
+    return 1'b1;
+  endfunction
+endmodule
diff --git a/test/systemverilog/function_automatic2.sv b/test/systemverilog/function_automatic2.sv
new file mode 100644
index 0000000000000000000000000000000000000000..c83d6e8c8848352e41235035631484186d0bee96
--- /dev/null
+++ b/test/systemverilog/function_automatic2.sv
@@ -0,0 +1,21 @@
+`define BITS  1
+`define BITS2 2
+
+module test;
+  function automatic logic [`BITS-1:0] extend_bxid(logic [`BITS2-1:0] coarse, logic [`BITS-1:0] current_bxid);
+
+    logic [`BITS-`BITS2-1:0] tmp;
+    logic [`BITS-`BITS2-1:0] tmp_m1;
+
+    tmp = current_bxid[`BITS-1:`BITS2];
+    tmp_m1 = tmp - 1;
+
+    if ({tmp, coarse} > current_bxid) return {tmp_m1, coarse};
+    else return {tmp, coarse};
+  endfunction
+
+  logic [`BITS2-1:0] a;
+  logic [`BITS-1 :0] b, c;
+  always_comb
+    c = extend_bxid(a,b);
+endmodule
diff --git a/test/test_tmrg.py b/test/test_tmrg.py
index ccd43c7732af392e41e402cc9e55c11c90bd4415..5c137e5f53e95420d0e0a8afd4e52cb5dcff7cf3 100644
--- a/test/test_tmrg.py
+++ b/test/test_tmrg.py
@@ -381,6 +381,8 @@ class TestTmrgOnSingleSystemVerilogFile():
             "systemverilog/forloop_generate01.sv",
             "systemverilog/forloop_generate02.sv",
             "systemverilog/function_automatic.sv",
+            "systemverilog/function_automatic1.sv",
+            "systemverilog/function_automatic2.sv",
             "systemverilog/function_static.sv",
             "systemverilog/rhs_assign.sv",
             "systemverilog/forinalways.sv",