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Created date
Resolve "TMRG blocking procedural assingment"
!151
· created
Oct 11, 2022
by
Matteo Lupi
FNAL wishlist
SystemVerilog
bug
confirmed
Merged
Approved
2
updated
Oct 12, 2022
Resolve "Incorrect output when port names are similar"
!109
· created
Apr 12, 2021
by
Szymon Kulis
bug
confirmed
Merged
0
updated
Apr 12, 2021
Resolve "Directive default_nettype not supported"
!98
· created
Dec 07, 2020
by
Szymon Kulis
bug
confirmed
Merged
Approved
3
updated
Dec 08, 2020
Resolve "Multiple for loops per generate block not supported"
!79
· created
Dec 02, 2019
by
Szymon Kulis
bug
confirmed
Merged
Approved
2
updated
Dec 03, 2019