Skip to content
GitLab
Explore
Sign in
tmrg
tmrg
Merge requests
Open
4
Merged
25
Closed
1
All
30
Actions
Subscribe to RSS feed
Recent searches
{{formattedKey}}
{{ title }}
{{ help }}
{{name}}
@{{username}}
None
Any
{{name}}
@{{username}}
None
Any
{{name}}
@{{username}}
None
Any
{{name}}
@{{username}}
None
Any
{{name}}
@{{username}}
None
Any
Upcoming
Started
{{title}}
None
Any
{{title}}
None
Any
{{title}}
None
Any
{{name}}
Yes
No
Yes
No
{{title}}
{{title}}
{{title}}
Updated date
Resolve "Add support for always_ff and asynchronous reset"
!138
· created
Feb 02, 2022
by
Matteo Lupi
FNAL wishlist
SystemVerilog
feature
Merged
Approved
0
updated
Feb 13, 2024
Resolve: Add integer type for inline assignment
!158
· created
Mar 17, 2023
by
Szymon Kulis
FNAL wishlist
bug
Merged
Approved
0
updated
Mar 20, 2023
Function automatic
!157
· created
Mar 16, 2023
by
Szymon Kulis
FNAL wishlist
bug
Merged
Approved
0
updated
Mar 17, 2023
Parameter integer
!156
· created
Mar 16, 2023
by
Szymon Kulis
FNAL wishlist
SystemVerilog
bug
Merged
Approved
0
updated
Mar 17, 2023
Resolve "TMRG blocking procedural assingment"
!151
· created
Oct 11, 2022
by
Matteo Lupi
FNAL wishlist
SystemVerilog
bug
confirmed
Merged
Approved
2
updated
Oct 12, 2022
Increased recursion limit for ECOND formatter
8 of 8 checklist items completed
!147
· created
Apr 04, 2022
by
Matteo Lupi
FNAL wishlist
Merged
Approved
0
updated
Apr 04, 2022
Resolve "TMRG inverts import/localparam order in triplicated file"
!142
· created
Feb 14, 2022
by
Matteo Lupi
FNAL wishlist
SystemVerilog
bug
Merged
Approved
6
updated
Feb 18, 2022
Resolve "Add support for unpacked arrays of packed arrays as localparam"
!139
· created
Feb 02, 2022
by
Matteo Lupi
FNAL wishlist
SystemVerilog
feature
Merged
Approved
0
updated
Feb 03, 2022
Add testcases
!128
· created
Jan 14, 2022
by
Matteo Lupi
FNAL wishlist
Merged
Approved
0
updated
Jan 28, 2022
Resolve "Add support for RHS casting"
!135
· created
Jan 21, 2022
by
Matteo Lupi
FNAL wishlist
SystemVerilog
feature
Merged
Approved
0
updated
Jan 28, 2022
Resolve "Add support for package parameters in I/O width"
!136
· created
Jan 24, 2022
by
Matteo Lupi
FNAL wishlist
SystemVerilog
feature
Merged
Approved
0
updated
Jan 28, 2022
Resolve "TMRG does not correctly triplicate generate-for loops for"
!137
· created
Jan 27, 2022
by
Szymon Kulis
FNAL wishlist
SystemVerilog
bug
Merged
Approved
1
updated
Jan 28, 2022
Resolve "Add support for Systemverilog localparam"
!134
· created
Jan 21, 2022
by
Matteo Lupi
FNAL wishlist
SystemVerilog
feature
Merged
Approved
2
updated
Jan 23, 2022
Resolve "Add support for unpacked arrays in ports declaration"
!130
· created
Jan 14, 2022
by
Matteo Lupi
FNAL wishlist
SystemVerilog
feature
Merged
Approved
5
updated
Jan 18, 2022
Resolve "Add support for unpacked arrays of packed arrays in port definition"
!131
· created
Jan 14, 2022
by
Matteo Lupi
FNAL wishlist
SystemVerilog
feature
Merged
Approved
3
updated
Jan 18, 2022
Resolve "Add support for sizes in unpacked array definition"
!129
· created
Jan 14, 2022
by
Matteo Lupi
FNAL wishlist
SystemVerilog
feature
Merged
Approved
3
updated
Jan 18, 2022
Resolve "Add support for cast in for-loop"
!132
· created
Jan 14, 2022
by
Matteo Lupi
FNAL wishlist
SystemVerilog
feature
Merged
Approved
4
updated
Jan 18, 2022
Resolve "Add support for '0 on RHS"
!124
· created
Aug 04, 2021
by
Matteo Lupi
FNAL wishlist
SystemVerilog
Merged
Approved
0
updated
Aug 09, 2021
Resolve "Add support for different `for` construct flavour"
!120
· created
Jul 29, 2021
by
Matteo Lupi
FNAL wishlist
SystemVerilog
Merged
Approved
13
updated
Aug 09, 2021
Resolve "Add support for `always_latch`"
!118
· created
Jul 29, 2021
by
Matteo Lupi
FNAL wishlist
SystemVerilog
Merged
Approved
0
updated
Jul 29, 2021
Prev
1
2
Next