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Updated date
Resolve "TMRG does not correctly triplicate generate-for loops for"
!137
· created
Jan 27, 2022
by
Szymon Kulis
FNAL wishlist
SystemVerilog
bug
Merged
Approved
1
updated
Jan 28, 2022
Add global entrypoint for gen_tmrg_libs.py
!95
· created
Jul 16, 2020
by
Stefan Biereigel
Merged
0
updated
Jan 27, 2022
Resolve "Add support for Systemverilog localparam"
!134
· created
Jan 21, 2022
by
Matteo Lupi
FNAL wishlist
SystemVerilog
feature
Merged
Approved
2
updated
Jan 23, 2022
Resolve "Add support for unpacked arrays in ports declaration"
!130
· created
Jan 14, 2022
by
Matteo Lupi
FNAL wishlist
SystemVerilog
feature
Merged
Approved
5
updated
Jan 18, 2022
Resolve "Add support for unpacked arrays of packed arrays in port definition"
!131
· created
Jan 14, 2022
by
Matteo Lupi
FNAL wishlist
SystemVerilog
feature
Merged
Approved
3
updated
Jan 18, 2022
Resolve "Add support for sizes in unpacked array definition"
!129
· created
Jan 14, 2022
by
Matteo Lupi
FNAL wishlist
SystemVerilog
feature
Merged
Approved
3
updated
Jan 18, 2022
Added support formal SEU injection
!127
· created
Nov 22, 2021
by
Matteo Lupi
feature
Merged
Approved
0
updated
Jan 18, 2022
Resolve "Add support for cast in for-loop"
!132
· created
Jan 14, 2022
by
Matteo Lupi
FNAL wishlist
SystemVerilog
feature
Merged
Approved
4
updated
Jan 18, 2022
Resolve "Add support for '0 on RHS"
!124
· created
Aug 04, 2021
by
Matteo Lupi
FNAL wishlist
SystemVerilog
Merged
Approved
0
updated
Aug 09, 2021
Resolve "Add support for different `for` construct flavour"
!120
· created
Jul 29, 2021
by
Matteo Lupi
FNAL wishlist
SystemVerilog
Merged
Approved
13
updated
Aug 09, 2021
Resolve "Add verible to CI for the `TestTmrgOnSingle*File` tests"
!122
· created
Jul 29, 2021
by
Matteo Lupi
SystemVerilog
Merged
Approved
10
updated
Aug 09, 2021
Fix typos
!125
· created
Aug 05, 2021
by
Matteo Lupi
documentation
Merged
Approved
0
updated
Aug 09, 2021
Resolve "Add support for `always_latch`"
!118
· created
Jul 29, 2021
by
Matteo Lupi
FNAL wishlist
SystemVerilog
Merged
Approved
0
updated
Jul 29, 2021
Resolve "Add support for `import <package_name>::<parameter>;`"
!119
· created
Jul 29, 2021
by
Matteo Lupi
FNAL wishlist
SystemVerilog
Merged
Approved
4
updated
Jul 29, 2021
Resolve "Add support for `always_comb`"
!117
· created
Jul 29, 2021
by
Matteo Lupi
FNAL wishlist
SystemVerilog
Merged
Approved
4
updated
Jul 29, 2021
Resolves "Add support for systemverilog `unique case` construct"
!114
· created
Jul 28, 2021
by
Szymon Kulis
FNAL wishlist
SystemVerilog
Merged
6
updated
Jul 29, 2021
Resolve "CI test does not check for syntax at end of test"
!121
· created
Jul 29, 2021
by
Matteo Lupi
Merged
Approved
1
updated
Jul 29, 2021
Resolve "Add support for `always_ff`"
!115
· created
Jul 28, 2021
by
Matteo Lupi
FNAL wishlist
SystemVerilog
Merged
Approved
4
updated
Jul 29, 2021
Add support for systemverilog `logic` construct
!113
· created
Jul 28, 2021
by
Matteo Lupi
FNAL wishlist
SystemVerilog
Merged
Approved
3
updated
Jul 29, 2021
Resolve "Add support for real input/output signals"
!116
· created
Jul 29, 2021
by
Szymon Kulis
feature
Merged
Approved
0
updated
Jul 29, 2021
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