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Created date
Remove dead code from the verilog parser
!93
· created
Jul 06, 2020
by
Szymon Kulis
Merged
0
updated
Jul 06, 2020
Resolve "Bug in processing nested generate/if statements"
!92
· created
Jul 06, 2020
by
Szymon Kulis
bug
Merged
3
updated
Jul 06, 2020
Bug fix in auto infering logic
!91
· created
Feb 26, 2020
by
Szymon Kulis
Merged
Approved
1
updated
Feb 26, 2020
Update gitignore file (filter egg files)
!90
· created
Feb 26, 2020
by
Szymon Kulis
Merged
Approved
0
updated
Feb 26, 2020
Resolve "Verilog simplification for SET injection"
!89
· created
Feb 13, 2020
by
Szymon Kulis
Merged
Approved
11
updated
Feb 14, 2020
Fix typo in verification example
!88
· created
Jan 28, 2020
by
Stefan Biereigel
Merged
Approved
0
updated
Jan 28, 2020
Resolve "Feature Request? Make tmrg recognize pre-triplicated blocks?"
!87
· created
Jan 22, 2020
by
Szymon Kulis
Merged
Approved
4
updated
Feb 13, 2020
fix .top reference in wrg
!86
· created
Jan 20, 2020
by
Stefan Biereigel
Merged
2
updated
Feb 04, 2020
Remove time offset in 36c3 video link
!85
· created
Jan 08, 2020
by
Stefan Biereigel
Merged
0
updated
Jan 08, 2020
Reference to 36c3 talk
!84
· created
Jan 06, 2020
by
Szymon Kulis
Merged
1
updated
Jan 06, 2020
Resolve "Feedthrough of non-triplicated signal produces redundant fanout+voter"
!83
· created
Dec 05, 2019
by
Szymon Kulis
Merged
2
updated
Dec 05, 2019
Code cleanup
!82
· created
Dec 04, 2019
by
Szymon Kulis
Merged
3
updated
Dec 05, 2019
Cleanup
!81
· created
Dec 03, 2019
by
Szymon Kulis
Merged
0
updated
Dec 03, 2019
Replace time.clock by time.process_time
!80
· created
Dec 02, 2019
by
Stefan Biereigel
Merged
0
updated
Dec 03, 2019
Resolve "Multiple for loops per generate block not supported"
!79
· created
Dec 02, 2019
by
Szymon Kulis
bug
confirmed
Merged
Approved
2
updated
Dec 03, 2019
tmrError wires/outputs improved
!78
· created
Nov 29, 2019
by
Szymon Kulis
Merged
Approved
2
updated
Nov 29, 2019
Allow modules without ports to be instantiated
!77
· created
Oct 29, 2019
by
Stefan Biereigel
Merged
Approved
1
updated
Oct 31, 2019
Resolve "Error with standard cell Verilog file when running command seeg"
!76
· created
Oct 09, 2019
by
Szymon Kulis
Merged
Approved
6
updated
Nov 29, 2019
LICENSE file updated
!75
· created
Sep 23, 2019
by
Szymon Kulis
Merged
0
updated
Sep 23, 2019
Fix gitlab.ci flow
!74
· created
Sep 23, 2019
by
Szymon Kulis
Merged
0
updated
Sep 23, 2019
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