- Put back Cmd FIFO reset in FW interface to avoid "Cmd FIFO errors"
- Larger log files: 16 Mb
- Fixed bug in optical readout in using different SFP connectors

- partial fix to FIFO error issue (lesser errors, no stuck FIFO)
- multiple averaged measurements of observables in monitoring now working properly
- more robust threshold adjustment with "golden section algorithm"

New features:

Multi-master
More robust thradj
Means for FW v4.07
Added skip initialisation sequence to CMSITminiDAQ
Small change in RD53Event: some fields changed meaning
Added a new user friendly way to pick up readout chip register values from txt file: see documentation pages 9 and 10

Container cannot be accessed by index anymore

Last tag in which containers can be accessed using the index

IT updates:
1. fixed bugs in latency scans in 4.12
2. working x-talk scans
3. possibility to configure data stream fields at runtime with xml file

IT: Change in the address table to support FW: 4.6

Implemented x-talk studies: either by manipulating the mask file (.txt) with the python program https://gitlab.cern.ch/cmsinnertracker/Ph2_ACF/-/blob/master/pythonUtils/pyUtilsIT/ManipulateITchipMask.py or by using options INJtype 4 or 5 as described in the usual documentation in the main gitlab page under Detailed description of the various calibrations

Working VoltageTuning procedure also for CROC

Better handling of runtime errors from decoding (no more crash)

Working voltage, currents, and temperatures readback

Changes from previous tag:
- fixed bug in making CROC masks
- fixed bug in writing LpGBT-v1.txt file
- added possibility to run scurves on a pixel pattern specified by the user with the txt file
- fixed bug in multi-threading of Running member function

Changes from the previous tag:
• added monitoring for RD53B (need to be tested)
• fixed bug in thradj related to masked pixels at exit (which shouldn't happen)
• fixed bug in masking pixels and PIX_MODE register which was wrongly set to zero due to the FW bug in the register readback
• implemented broadcast for RD53B
• implemented DoDataIntegrity check before PixelAlive, allows detecting broken CoreColumns causing data integrity failure
• Implemented dual-slope fit for RD3B

v4-08
Compatible IT-FW: https://gitlab.cern.ch/cmstkph2-IT/d19c-firmware/-/releases/v4.5_IT-uDTC_fw

v4-07
Compatible OT-FW: https://udtc-ot-firmware.web.cern.ch/?dir=v0.1-OT 
Compatible IT-FW: https://gitlab.cern.ch/cmstkph2-IT/d19c-firmware/-/releases/v4.5_IT-uDTC_fw

Working at the TIF with single module calibrations in preparation for OT Magnet Test Aug 2022.

DDR3 now is a circular buffer
Support for LpGBTv1 included
Support for all possible optical mapping configurations included
Started porting CROC development

IT code compatible with FW tag 4.4

Last Tag before Common Processor Block

Last tag supporting for CBC8 modules

Working at best before Merging back to Dev

Ph2_ACF tag v4-02

The HW supported by the tag is

RD53 single and multiple chip (Linear front-end only)

added support for optical readout
added automatic Rx phase adjustment


2CBC3
8CBC3
8CBC3 + CIC v1
8CBC3 + CIC v2
2S optical readout via GBTx (single module)
LpGBT
Multiplex crate
SSA
MPA (preliminary)
power supply support (preliminary)

The corresponding FW can be found at

https://cernbox.cern.ch/index.php/apps/files/?dir=/__myshares/FWtags%20(id%3A246063)/FW_v4_01&

in order to have access to the FW repository you should subscribe to the cms-tracker-phase2-DAQ e-group