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mergeVMK180
02fbcaee
·
Removed unused IP cores
·
Sep 23, 2024
crc_err_inj
7ad006fc
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Added CRC error inject signals (now flips CRC24/32 bit 7 by XOR with logic '1')
·
Sep 09, 2024
mergeVMK180_ila
54ca3802
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Removed the GTM reset VIO and instead connected the reset_all to the TX/RX GTM...
·
Aug 13, 2024
encoder_improvements
51fe0cae
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Minor data generator fix for VUnit tb
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Jul 31, 2024
axis_tuser_sync
63030191
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Synchronized tuser(0) crc-error signal to m_axis.tlast output
·
Jul 19, 2024
Stale branches
InterlakenChannelBondingMux
e738439c
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Changed data generator to Xilinx Interlaken core
·
Feb 23, 2021
fbonini/IBUFDSGT
a3c2b138
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remving retiming attributes
·
Jul 07, 2021
BNL181_interlaken
d9514327
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Support multiple reference clocks for Virtex Ultrascale+
·
Mar 02, 2022
!7
VersalVMK180_interlaken
cab14256
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Update the location of bd .tcl files
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Apr 20, 2022
mergeVMKVCUtest
ee341676
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Added more sources, ip-cores and made some improvements (reset)
·
Jun 28, 2022