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atlas-tdaq-felix
Core1990_Interlaken
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07cd2fe0
·
Merge branch 'encoder_improvements' in 'master'
·
May 27, 2024
encoder_improvements
95b1f23d
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Removed old block sync from GTY and fileset
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May 27, 2024
status_signals
ad95afa9
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Updated UVVM tb file (added initial values)
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May 16, 2024
FLX-2382_master
fde7de52
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Removed branch specific content for better compatibility with master
·
Apr 23, 2024
FLX-2383_Core1990_lint
24ecbe8f
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Import VHDL files as VHDL-2008 now
·
Apr 22, 2024
Stale branches
InterlakenChannelBondingMux
e738439c
·
Changed data generator to Xilinx Interlaken core
·
Feb 23, 2021
fbonini/IBUFDSGT
a3c2b138
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remving retiming attributes
·
Jul 07, 2021
BNL181_interlaken
d9514327
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Support multiple reference clocks for Virtex Ultrascale+
·
Mar 02, 2022
!7
VersalVMK180_interlaken
cab14256
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Update the location of bd .tcl files
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Apr 20, 2022
mergeVMKVCUtest
ee341676
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Added more sources, ip-cores and made some improvements (reset)
·
Jun 28, 2022