SimpleFromHostFifo.vhd

--! This file is part of the FELIX firmware distribution (https://gitlab.cern.ch/atlas-tdaq-felix/firmware/).
--! Copyright (C) 2001-2021 CERN for the benefit of the ATLAS collaboration.
--! Authors:
--!               Marius Wensing
--!               Frans Schreuder
--! 
--!   Licensed under the Apache License, Version 2.0 (the "License");
--!   you may not use this file except in compliance with the License.
--!   You may obtain a copy of the License at
--!
--!       http://www.apache.org/licenses/LICENSE-2.0
--!
--!   Unless required by applicable law or agreed to in writing, software
--!   distributed under the License is distributed on an "AS IS" BASIS,
--!   WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
--!   See the License for the specific language governing permissions and
--!   limitations under the License.

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;

library XPM;
use XPM.VCOMPONENTS.ALL;

entity SimpleFromHostFifo is
	generic (
		WIDTH : integer := 256;
		DEPTH : integer := 64
	);
	port (
		clk : in std_logic;
		reset : in std_logic;
		din : in std_logic_vector(WIDTH-1 downto 0);
		dout : out std_logic_vector(WIDTH-1 downto 0);
		wren : in std_logic;
		rden : in std_logic;
		full : out std_logic;
		empty : out std_logic
	);
end SimpleFromHostFifo;

architecture rtl of SimpleFromHostFifo is
begin

fifo: xpm_fifo_sync
	generic map (
		DOUT_RESET_VALUE => "0",
		ECC_MODE => "no_ecc",
		FIFO_MEMORY_TYPE => "block",
		FIFO_READ_LATENCY => 1,
		FIFO_WRITE_DEPTH => DEPTH,
		FULL_RESET_VALUE => 0,
		PROG_EMPTY_THRESH => 10,
		PROG_FULL_THRESH => 10,
		RD_DATA_COUNT_WIDTH => 1,
		READ_DATA_WIDTH => WIDTH,
		READ_MODE => "std",
		USE_ADV_FEATURES => "0000",
		WAKEUP_TIME => 0,
		WRITE_DATA_WIDTH => WIDTH,
		WR_DATA_COUNT_WIDTH => 1
	)
	port map (
		almost_empty => open,
		almost_full => open,
		data_valid => open,
		dbiterr => open,
		dout => dout,
		empty => empty,
		full => full,
		overflow => open,
		prog_empty => open,
		prog_full => open,
		rd_data_count => open,
		rd_rst_busy => open,
		sbiterr => open,
		underflow => open,
		wr_ack => open,
		wr_data_count => open,
		wr_rst_busy => open,
		din => din,
		injectdbiterr => '0',
		injectsbiterr => '0',
		rd_en => rden,
		rst => reset,
		sleep => '0',
		wr_clk => clk,
		wr_en => wren
	);

end architecture;