Skip to content
Snippets Groups Projects
Commit 019813c3 authored by Frans Schreuder's avatar Frans Schreuder
Browse files

Fix for FLX-2381: Drive disabled bits of EPROC_OUT to "01"

parent 4757dca5
No related branches found
No related tags found
1 merge request!536Only reset Central Router FIFOs when clk40 is guaranteed to be stable, and...
Pipeline #7238341 passed
Stage: sim
    Stage: build_full
      Stage: build_gbt_8ch
        Hide whitespace changes
        Inline Side-by-side
        simulation/UVVMExample/tb/centralRouter_tb.vhd
        + 19
        − 4
        View file @ 019813c3
        ...@@ -201,6 +201,21 @@ begin ...@@ -201,6 +201,21 @@ begin
        register_map_40_control.CR_TOHOST_EGROUP_CTRL(i)(4).MAX_CHUNK_LEN <= "001001001001"; --Set all to 512 bytes, or 15 for HDLC register_map_40_control.CR_TOHOST_EGROUP_CTRL(i)(4).MAX_CHUNK_LEN <= "001001001001"; --Set all to 512 bytes, or 15 for HDLC
        register_map_40_control.CR_TOHOST_EGROUP_CTRL(i)(4).INSTANT_TIMEOUT_ENA <= "11111111"; register_map_40_control.CR_TOHOST_EGROUP_CTRL(i)(4).INSTANT_TIMEOUT_ENA <= "11111111";
        register_map_40_control.CR_FROMHOST_EGROUP_CTRL(i)(0).EPROC_ENA <= "000000000000000"; --2b elinks
        register_map_40_control.CR_FROMHOST_EGROUP_CTRL(i)(1).EPROC_ENA <= "000000000000000"; --2b elinks
        register_map_40_control.CR_FROMHOST_EGROUP_CTRL(i)(2).EPROC_ENA <= "000000000000000"; --2b elinks
        register_map_40_control.CR_FROMHOST_EGROUP_CTRL(i)(3).EPROC_ENA <= "000000000000000"; --2b elinks
        register_map_40_control.CR_FROMHOST_EGROUP_CTRL(i)(4).EPROC_ENA <= "000000000000000"; --2b elinks
        register_map_40_control.CR_FROMHOST_EGROUP_CTRL(i)(0).PATH_ENCODING <= x"00000000";
        register_map_40_control.CR_FROMHOST_EGROUP_CTRL(i)(1).PATH_ENCODING <= x"00000000";
        register_map_40_control.CR_FROMHOST_EGROUP_CTRL(i)(2).PATH_ENCODING <= x"00000000";
        register_map_40_control.CR_FROMHOST_EGROUP_CTRL(i)(3).PATH_ENCODING <= x"00000000";
        register_map_40_control.CR_FROMHOST_EGROUP_CTRL(i)(4).PATH_ENCODING <= x"00000000";
        register_map_40_control.CR_FROMHOST_EGROUP_CTRL(i)(0).REVERSE_ELINKS <= x"00";
        register_map_40_control.CR_FROMHOST_EGROUP_CTRL(i)(1).REVERSE_ELINKS <= x"00";
        register_map_40_control.CR_FROMHOST_EGROUP_CTRL(i)(2).REVERSE_ELINKS <= x"00";
        register_map_40_control.CR_FROMHOST_EGROUP_CTRL(i)(3).REVERSE_ELINKS <= x"00";
        register_map_40_control.CR_FROMHOST_EGROUP_CTRL(i)(4).REVERSE_ELINKS <= x"00";
        end loop; end loop;
        wait; wait;
        ...@@ -296,10 +311,10 @@ generic map( ...@@ -296,10 +311,10 @@ generic map(
        EnableFrHo_Egroup0Eproc2_8b10b => true, EnableFrHo_Egroup0Eproc2_8b10b => true,
        EnableFrHo_Egroup0Eproc4_8b10b => true, EnableFrHo_Egroup0Eproc4_8b10b => true,
        EnableFrHo_Egroup0Eproc8_8b10b => true, EnableFrHo_Egroup0Eproc8_8b10b => true,
        EnableFrHo_Egroup1Eproc2_HDLC => true, EnableFrHo_Egroup1Eproc2_HDLC => false,
        EnableFrHo_Egroup1Eproc2_8b10b => true, EnableFrHo_Egroup1Eproc2_8b10b => false,
        EnableFrHo_Egroup1Eproc4_8b10b => true, EnableFrHo_Egroup1Eproc4_8b10b => false,
        EnableFrHo_Egroup1Eproc8_8b10b => true, EnableFrHo_Egroup1Eproc8_8b10b => false,
        EnableFrHo_Egroup2Eproc2_HDLC => true, EnableFrHo_Egroup2Eproc2_HDLC => true,
        EnableFrHo_Egroup2Eproc2_8b10b => true, EnableFrHo_Egroup2Eproc2_8b10b => true,
        EnableFrHo_Egroup2Eproc4_8b10b => true, EnableFrHo_Egroup2Eproc4_8b10b => true,
        ......
        sources/centralRouter/EPROC_OUT2.vhd
        + 7
        − 5
        View file @ 019813c3
        ...@@ -199,7 +199,7 @@ Enc_8b10b_disable: if ( ...@@ -199,7 +199,7 @@ Enc_8b10b_disable: if (
        ) generate ) generate
        getDataTrig_ENC8b10b_case <= '0'; getDataTrig_ENC8b10b_case <= '0';
        EdataOUT_ENC8b10b_case <= "00"; EdataOUT_ENC8b10b_case <= "01";
        end generate Enc_8b10b_disable; end generate Enc_8b10b_disable;
        ...@@ -255,7 +255,7 @@ HDLC_disable: if ( ...@@ -255,7 +255,7 @@ HDLC_disable: if (
        ) generate ) generate
        getDataTrig_HDLC_case <= '0'; getDataTrig_HDLC_case <= '0';
        EdataOUT_HDLC_case <= "00"; EdataOUT_HDLC_case <= "01";
        end generate HDLC_disable; end generate HDLC_disable;
        end generate HDLC_almost_disable; end generate HDLC_almost_disable;
        ...@@ -302,7 +302,7 @@ Module_disable: if ( ...@@ -302,7 +302,7 @@ Module_disable: if (
        (includeNoEncodingCase = false)) (includeNoEncodingCase = false))
        ) generate ) generate
        edata_out_s <= (others=>'0'); edata_out_s <= "01";
        getDataTrig <= '0'; getDataTrig <= '0';
        end generate Module_disable; end generate Module_disable;
        ...@@ -370,11 +370,13 @@ port map( ...@@ -370,11 +370,13 @@ port map(
        -- --
        out_sel: process(swap_outbits,ao_edata_out) out_sel: process(swap_outbits,ao_edata_out)
        begin begin
        if swap_outbits = '1' then if ENA = '0' then
        EDATA_OUT <= "01";
        elsif swap_outbits = '1' then
        EDATA_OUT <= ao_edata_out(0) & ao_edata_out(1); EDATA_OUT <= ao_edata_out(0) & ao_edata_out(1);
        else else
        EDATA_OUT <= ao_edata_out; EDATA_OUT <= ao_edata_out;
        end if; end if;
        end process; end process;
        -- --
        ......
        0% or .
        You are about to add 0 people to the discussion. Proceed with caution.
        Finish editing this message first!
        Please register or to comment