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Commit 3b5bb43a authored by Frans Schreuder's avatar Frans Schreuder
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Changed strips build to CPLL

parent 41a5694f
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1 merge request!570Phase2/release 5.1
Pipeline #7742810 passed
Stage: vsg
    Stage: sim
      Stage: build_full_gbt_4ch
        Stage: build_strip_pixel_4ch
          Stage: build_lpgbt_bcmp_4ch
            Stage: build_interlaken_8ch
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              scripts/FELIX_top/do_implementation_BNL712_strips_24ch.tcl
              + 2
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              View file @ 3b5bb43a
              ...@@ -28,6 +28,8 @@ set app_clk_freq 200 ...@@ -28,6 +28,8 @@ set app_clk_freq 200
              set ENDPOINTS 2 set ENDPOINTS 2
              set GTREFCLKS 5 set GTREFCLKS 5
              set PLL_SEL $CPLL
              set FIRMWARE_MODE $FIRMWARE_MODE_STRIP set FIRMWARE_MODE $FIRMWARE_MODE_STRIP
              #Tell elinkconfig that only 4 and 8-bit decoding is allowed #Tell elinkconfig that only 4 and 8-bit decoding is allowed
              ......
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